Lines Matching +full:rs485 +full:- +full:rts +full:- +full:active +full:- +full:low
1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
13 #include <linux/dma-mapping.h>
29 /* All registers are 8-bit width */
118 /* 32-bit global registers only for i.MX7ULP/i.MX8x
123 /* 32-bit register definition */
244 #define DRIVER_NAME "fsl-lpuart"
337 .rx_watermark = 7, /* A lower watermark is ideal for low baud rates. */
347 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
348 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
349 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
350 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
351 { .compatible = "fsl,imx8ulp-lpuart", .data = &imx8ulp_data, },
352 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
353 { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data},
363 return (sport->devtype == LS1021A_LPUART || in is_layerscape_lpuart()
364 sport->devtype == LS1028A_LPUART); in is_layerscape_lpuart()
369 return sport->devtype == IMX7ULP_LPUART; in is_imx7ulp_lpuart()
374 return sport->devtype == IMX8ULP_LPUART; in is_imx8ulp_lpuart()
379 return sport->devtype == IMX8QXP_LPUART; in is_imx8qxp_lpuart()
384 switch (port->iotype) { in lpuart32_read()
386 return readl(port->membase + off); in lpuart32_read()
388 return ioread32be(port->membase + off); in lpuart32_read()
397 switch (port->iotype) { in lpuart32_write()
399 writel(val, port->membase + off); in lpuart32_write()
402 iowrite32be(val, port->membase + off); in lpuart32_write()
412 ret = clk_prepare_enable(sport->ipg_clk); in __lpuart_enable_clks()
416 ret = clk_prepare_enable(sport->baud_clk); in __lpuart_enable_clks()
418 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
422 clk_disable_unprepare(sport->baud_clk); in __lpuart_enable_clks()
423 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
432 return clk_get_rate(sport->baud_clk); in lpuart_get_baud_clk_rate()
434 return clk_get_rate(sport->ipg_clk); in lpuart_get_baud_clk_rate()
444 temp = readb(port->membase + UARTCR2); in lpuart_stop_tx()
446 writeb(temp, port->membase + UARTCR2); in lpuart_stop_tx()
462 temp = readb(port->membase + UARTCR2); in lpuart_stop_rx()
463 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); in lpuart_stop_rx()
476 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart_dma_tx()
477 struct scatterlist *sgl = sport->tx_sgl; in lpuart_dma_tx()
478 struct device *dev = sport->port.dev; in lpuart_dma_tx()
479 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx()
482 if (sport->dma_tx_in_progress) in lpuart_dma_tx()
485 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); in lpuart_dma_tx()
487 if (xmit->tail < xmit->head || xmit->head == 0) { in lpuart_dma_tx()
488 sport->dma_tx_nents = 1; in lpuart_dma_tx()
489 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); in lpuart_dma_tx()
491 sport->dma_tx_nents = 2; in lpuart_dma_tx()
493 sg_set_buf(sgl, xmit->buf + xmit->tail, in lpuart_dma_tx()
494 UART_XMIT_SIZE - xmit->tail); in lpuart_dma_tx()
495 sg_set_buf(sgl + 1, xmit->buf, xmit->head); in lpuart_dma_tx()
498 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
505 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, in lpuart_dma_tx()
508 if (!sport->dma_tx_desc) { in lpuart_dma_tx()
509 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
515 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; in lpuart_dma_tx()
516 sport->dma_tx_desc->callback_param = sport; in lpuart_dma_tx()
517 sport->dma_tx_in_progress = true; in lpuart_dma_tx()
518 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); in lpuart_dma_tx()
524 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port); in lpuart_stopped_or_empty()
530 struct scatterlist *sgl = &sport->tx_sgl[0]; in lpuart_dma_tx_complete()
531 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart_dma_tx_complete()
532 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx_complete()
535 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_dma_tx_complete()
536 if (!sport->dma_tx_in_progress) { in lpuart_dma_tx_complete()
537 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_dma_tx_complete()
541 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx_complete()
544 uart_xmit_advance(&sport->port, sport->dma_tx_bytes); in lpuart_dma_tx_complete()
545 sport->dma_tx_in_progress = false; in lpuart_dma_tx_complete()
546 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_dma_tx_complete()
549 uart_write_wakeup(&sport->port); in lpuart_dma_tx_complete()
551 if (waitqueue_active(&sport->dma_wait)) { in lpuart_dma_tx_complete()
552 wake_up(&sport->dma_wait); in lpuart_dma_tx_complete()
556 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_dma_tx_complete()
558 if (!lpuart_stopped_or_empty(&sport->port)) in lpuart_dma_tx_complete()
561 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_dma_tx_complete()
566 switch (sport->port.iotype) { in lpuart_dma_datareg_addr()
568 return sport->port.mapbase + UARTDATA; in lpuart_dma_datareg_addr()
570 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; in lpuart_dma_datareg_addr()
572 return sport->port.mapbase + UARTDR; in lpuart_dma_datareg_addr()
586 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); in lpuart_dma_tx_request()
589 dev_err(sport->port.dev, in lpuart_dma_tx_request()
599 return sport->port.iotype == UPIO_MEM32 || in lpuart_is_32()
600 sport->port.iotype == UPIO_MEM32BE; in lpuart_is_32()
606 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_flush_buffer()
609 if (sport->lpuart_dma_tx_use) { in lpuart_flush_buffer()
610 if (sport->dma_tx_in_progress) { in lpuart_flush_buffer()
611 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], in lpuart_flush_buffer()
612 sport->dma_tx_nents, DMA_TO_DEVICE); in lpuart_flush_buffer()
613 sport->dma_tx_in_progress = false; in lpuart_flush_buffer()
619 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart_flush_buffer()
621 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart_flush_buffer()
623 val = readb(sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
625 writeb(val, sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
632 while (!(readb(port->membase + offset) & bit)) in lpuart_wait_bit_set()
652 sport->port.fifosize = 0; in lpuart_poll_init()
654 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_poll_init()
656 writeb(0, sport->port.membase + UARTCR2); in lpuart_poll_init()
658 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_poll_init()
661 sport->port.membase + UARTPFIFO); in lpuart_poll_init()
665 sport->port.membase + UARTCFIFO); in lpuart_poll_init()
668 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_poll_init()
669 readb(sport->port.membase + UARTDR); in lpuart_poll_init()
670 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_poll_init()
673 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_poll_init()
674 writeb(1, sport->port.membase + UARTRWFIFO); in lpuart_poll_init()
677 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); in lpuart_poll_init()
678 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_poll_init()
687 writeb(c, port->membase + UARTDR); in lpuart_poll_put_char()
692 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) in lpuart_poll_get_char()
695 return readb(port->membase + UARTDR); in lpuart_poll_get_char()
704 sport->port.fifosize = 0; in lpuart32_poll_init()
706 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_poll_init()
709 lpuart32_write(&sport->port, 0, UARTCTRL); in lpuart32_poll_init()
711 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_poll_init()
714 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); in lpuart32_poll_init()
717 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); in lpuart32_poll_init()
720 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { in lpuart32_poll_init()
721 lpuart32_read(&sport->port, UARTDATA); in lpuart32_poll_init()
722 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); in lpuart32_poll_init()
726 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); in lpuart32_poll_init()
727 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_poll_init()
749 struct uart_port *port = &sport->port; in lpuart_transmit_buffer()
753 readb(port->membase + UARTTCFIFO) < sport->txfifo_size, in lpuart_transmit_buffer()
754 writeb(ch, port->membase + UARTDR)); in lpuart_transmit_buffer()
759 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart32_transmit_buffer()
762 if (sport->port.x_char) { in lpuart32_transmit_buffer()
763 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); in lpuart32_transmit_buffer()
764 sport->port.icount.tx++; in lpuart32_transmit_buffer()
765 sport->port.x_char = 0; in lpuart32_transmit_buffer()
769 if (lpuart_stopped_or_empty(&sport->port)) { in lpuart32_transmit_buffer()
770 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
774 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
777 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { in lpuart32_transmit_buffer()
778 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); in lpuart32_transmit_buffer()
779 uart_xmit_advance(&sport->port, 1); in lpuart32_transmit_buffer()
780 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
786 uart_write_wakeup(&sport->port); in lpuart32_transmit_buffer()
789 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
798 temp = readb(port->membase + UARTCR2); in lpuart_start_tx()
799 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); in lpuart_start_tx()
801 if (sport->lpuart_dma_tx_use) { in lpuart_start_tx()
805 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) in lpuart_start_tx()
815 if (sport->lpuart_dma_tx_use) { in lpuart32_start_tx()
832 pm_runtime_mark_last_busy(port->dev); in lpuart_uart_pm()
833 pm_runtime_put_autosuspend(port->dev); in lpuart_uart_pm()
836 pm_runtime_get_sync(port->dev); in lpuart_uart_pm()
846 unsigned char sr1 = readb(port->membase + UARTSR1); in lpuart_tx_empty()
847 unsigned char sfifo = readb(port->membase + UARTSFIFO); in lpuart_tx_empty()
849 if (sport->dma_tx_in_progress) in lpuart_tx_empty()
866 if (sport->dma_tx_in_progress) in lpuart32_tx_empty()
882 spin_lock(&sport->port.lock); in lpuart_txint()
884 spin_unlock(&sport->port.lock); in lpuart_txint()
890 struct tty_port *port = &sport->port.state->port; in lpuart_rxint()
893 spin_lock(&sport->port.lock); in lpuart_rxint()
895 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { in lpuart_rxint()
897 sport->port.icount.rx++; in lpuart_rxint()
902 sr = readb(sport->port.membase + UARTSR1); in lpuart_rxint()
903 rx = readb(sport->port.membase + UARTDR); in lpuart_rxint()
905 if (uart_prepare_sysrq_char(&sport->port, rx)) in lpuart_rxint()
910 sport->port.icount.parity++; in lpuart_rxint()
912 sport->port.icount.frame++; in lpuart_rxint()
917 if (sr & sport->port.ignore_status_mask) { in lpuart_rxint()
923 sr &= sport->port.read_status_mask; in lpuart_rxint()
933 sport->port.sysrq = 0; in lpuart_rxint()
937 sport->port.icount.buf_overrun++; in lpuart_rxint()
942 sport->port.icount.overrun += overrun; in lpuart_rxint()
948 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_rxint()
949 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); in lpuart_rxint()
952 uart_unlock_and_check_sysrq(&sport->port); in lpuart_rxint()
959 spin_lock(&sport->port.lock); in lpuart32_txint()
961 spin_unlock(&sport->port.lock); in lpuart32_txint()
967 struct tty_port *port = &sport->port.state->port; in lpuart32_rxint()
971 spin_lock(&sport->port.lock); in lpuart32_rxint()
973 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { in lpuart32_rxint()
975 sport->port.icount.rx++; in lpuart32_rxint()
980 sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_rxint()
981 rx = lpuart32_read(&sport->port, UARTDATA); in lpuart32_rxint()
990 if (is_break && uart_handle_break(&sport->port)) in lpuart32_rxint()
993 if (uart_prepare_sysrq_char(&sport->port, rx)) in lpuart32_rxint()
998 sport->port.icount.parity++; in lpuart32_rxint()
1001 sport->port.icount.brk++; in lpuart32_rxint()
1003 sport->port.icount.frame++; in lpuart32_rxint()
1007 sport->port.icount.overrun++; in lpuart32_rxint()
1009 if (sr & sport->port.ignore_status_mask) { in lpuart32_rxint()
1015 sr &= sport->port.read_status_mask; in lpuart32_rxint()
1030 if (sport->is_cs7) in lpuart32_rxint()
1034 sport->port.icount.buf_overrun++; in lpuart32_rxint()
1038 uart_unlock_and_check_sysrq(&sport->port); in lpuart32_rxint()
1048 sts = readb(sport->port.membase + UARTSR1); in lpuart_int()
1051 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { in lpuart_int()
1052 readb(sport->port.membase + UARTDR); in lpuart_int()
1053 uart_handle_break(&sport->port); in lpuart_int()
1055 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_int()
1059 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) in lpuart_int()
1062 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) in lpuart_int()
1071 while (count--) { in lpuart_handle_sysrq_chars()
1080 struct circ_buf *ring = &sport->rx_ring; in lpuart_handle_sysrq()
1083 if (ring->head < ring->tail) { in lpuart_handle_sysrq()
1084 count = sport->rx_sgl.length - ring->tail; in lpuart_handle_sysrq()
1085 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1086 ring->buf + ring->tail, count); in lpuart_handle_sysrq()
1087 ring->tail = 0; in lpuart_handle_sysrq()
1090 if (ring->head > ring->tail) { in lpuart_handle_sysrq()
1091 count = ring->head - ring->tail; in lpuart_handle_sysrq()
1092 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1093 ring->buf + ring->tail, count); in lpuart_handle_sysrq()
1094 ring->tail = ring->head; in lpuart_handle_sysrq()
1111 struct tty_port *port = &sport->port.state->port; in lpuart_copy_rx_to_tty()
1114 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_copy_rx_to_tty()
1115 struct circ_buf *ring = &sport->rx_ring; in lpuart_copy_rx_to_tty()
1120 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart_copy_rx_to_tty()
1124 lpuart32_write(&sport->port, sr, UARTSTAT); in lpuart_copy_rx_to_tty()
1127 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1129 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1132 unsigned char sr = readb(sport->port.membase + UARTSR1); in lpuart_copy_rx_to_tty()
1138 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1140 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1143 readb(sport->port.membase + UARTDR); in lpuart_copy_rx_to_tty()
1146 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1148 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1158 if (readb(sport->port.membase + UARTSFIFO) & in lpuart_copy_rx_to_tty()
1161 sport->port.membase + UARTSFIFO); in lpuart_copy_rx_to_tty()
1163 sport->port.membase + UARTCFIFO); in lpuart_copy_rx_to_tty()
1167 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1171 async_tx_ack(sport->dma_rx_desc); in lpuart_copy_rx_to_tty()
1173 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1175 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart_copy_rx_to_tty()
1177 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart_copy_rx_to_tty()
1178 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1183 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1187 * ring->head points to the end of data already written by the DMA. in lpuart_copy_rx_to_tty()
1188 * ring->tail points to the beginning of data to be read by the in lpuart_copy_rx_to_tty()
1193 ring->head = sport->rx_sgl.length - state.residue; in lpuart_copy_rx_to_tty()
1194 BUG_ON(ring->head > sport->rx_sgl.length); in lpuart_copy_rx_to_tty()
1199 if (sport->port.sysrq) { in lpuart_copy_rx_to_tty()
1205 * At this point ring->head may point to the first byte right after the in lpuart_copy_rx_to_tty()
1207 * 0 <= ring->head <= sport->rx_sgl.length in lpuart_copy_rx_to_tty()
1209 * However ring->tail must always points inside the dma buffer: in lpuart_copy_rx_to_tty()
1210 * 0 <= ring->tail <= sport->rx_sgl.length - 1 in lpuart_copy_rx_to_tty()
1216 if (ring->head < ring->tail) { in lpuart_copy_rx_to_tty()
1217 count = sport->rx_sgl.length - ring->tail; in lpuart_copy_rx_to_tty()
1219 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, in lpuart_copy_rx_to_tty()
1220 count, sport->is_cs7); in lpuart_copy_rx_to_tty()
1222 sport->port.icount.buf_overrun++; in lpuart_copy_rx_to_tty()
1223 ring->tail = 0; in lpuart_copy_rx_to_tty()
1224 sport->port.icount.rx += copied; in lpuart_copy_rx_to_tty()
1228 if (ring->tail < ring->head) { in lpuart_copy_rx_to_tty()
1229 count = ring->head - ring->tail; in lpuart_copy_rx_to_tty()
1230 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail, in lpuart_copy_rx_to_tty()
1231 count, sport->is_cs7); in lpuart_copy_rx_to_tty()
1233 sport->port.icount.buf_overrun++; in lpuart_copy_rx_to_tty()
1234 /* Wrap ring->head if needed */ in lpuart_copy_rx_to_tty()
1235 if (ring->head >= sport->rx_sgl.length) in lpuart_copy_rx_to_tty()
1236 ring->head = 0; in lpuart_copy_rx_to_tty()
1237 ring->tail = ring->head; in lpuart_copy_rx_to_tty()
1238 sport->port.icount.rx += copied; in lpuart_copy_rx_to_tty()
1241 sport->last_residue = state.residue; in lpuart_copy_rx_to_tty()
1244 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1247 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1250 if (!sport->dma_idle_int) in lpuart_copy_rx_to_tty()
1251 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); in lpuart_copy_rx_to_tty()
1264 struct dma_chan *chan = sport->dma_rx_chan; in lpuart32_dma_idleint()
1265 struct circ_buf *ring = &sport->rx_ring; in lpuart32_dma_idleint()
1269 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart32_dma_idleint()
1271 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart32_dma_idleint()
1275 ring->head = sport->rx_sgl.length - state.residue; in lpuart32_dma_idleint()
1276 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); in lpuart32_dma_idleint()
1288 sts = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_int()
1289 rxcount = lpuart32_read(&sport->port, UARTWATER); in lpuart32_int()
1292 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) in lpuart32_int()
1295 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) in lpuart32_int()
1298 if ((sts & UARTSTAT_IDLE) && sport->lpuart_dma_rx_use && sport->dma_idle_int) in lpuart32_int()
1301 lpuart32_write(&sport->port, sts, UARTSTAT); in lpuart32_int()
1316 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_timer_func()
1317 struct circ_buf *ring = &sport->rx_ring; in lpuart_timer_func()
1322 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart_timer_func()
1324 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart_timer_func()
1328 ring->head = sport->rx_sgl.length - state.residue; in lpuart_timer_func()
1329 count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length); in lpuart_timer_func()
1332 if ((count != 0) && (sport->last_residue == state.residue)) in lpuart_timer_func()
1335 mod_timer(&sport->lpuart_timer, in lpuart_timer_func()
1336 jiffies + sport->dma_rx_timeout); in lpuart_timer_func()
1338 if (spin_trylock_irqsave(&sport->port.lock, flags)) { in lpuart_timer_func()
1339 sport->last_residue = state.residue; in lpuart_timer_func()
1340 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_timer_func()
1347 struct circ_buf *ring = &sport->rx_ring; in lpuart_start_rx_dma()
1349 struct tty_port *port = &sport->port.state->port; in lpuart_start_rx_dma()
1350 struct tty_struct *tty = port->tty; in lpuart_start_rx_dma()
1351 struct ktermios *termios = &tty->termios; in lpuart_start_rx_dma()
1352 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_start_rx_dma()
1353 unsigned int bits = tty_get_frame_size(termios->c_cflag); in lpuart_start_rx_dma()
1360 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; in lpuart_start_rx_dma()
1361 sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len)); in lpuart_start_rx_dma()
1362 sport->rx_dma_rng_buf_len = max_t(int, in lpuart_start_rx_dma()
1363 sport->rxfifo_size * 2, in lpuart_start_rx_dma()
1364 sport->rx_dma_rng_buf_len); in lpuart_start_rx_dma()
1369 if (sport->rx_dma_rng_buf_len < 16) in lpuart_start_rx_dma()
1370 sport->rx_dma_rng_buf_len = 16; in lpuart_start_rx_dma()
1372 sport->last_residue = 0; in lpuart_start_rx_dma()
1373 sport->dma_rx_timeout = max(nsecs_to_jiffies( in lpuart_start_rx_dma()
1374 sport->port.frame_time * DMA_RX_IDLE_CHARS), 1UL); in lpuart_start_rx_dma()
1376 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); in lpuart_start_rx_dma()
1377 if (!ring->buf) in lpuart_start_rx_dma()
1378 return -ENOMEM; in lpuart_start_rx_dma()
1380 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); in lpuart_start_rx_dma()
1381 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, in lpuart_start_rx_dma()
1385 dev_err(sport->port.dev, "DMA Rx mapping error\n"); in lpuart_start_rx_dma()
1386 return -EINVAL; in lpuart_start_rx_dma()
1396 dev_err(sport->port.dev, in lpuart_start_rx_dma()
1401 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, in lpuart_start_rx_dma()
1402 sg_dma_address(&sport->rx_sgl), in lpuart_start_rx_dma()
1403 sport->rx_sgl.length, in lpuart_start_rx_dma()
1404 sport->rx_sgl.length / 2, in lpuart_start_rx_dma()
1407 if (!sport->dma_rx_desc) { in lpuart_start_rx_dma()
1408 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); in lpuart_start_rx_dma()
1409 return -EFAULT; in lpuart_start_rx_dma()
1412 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; in lpuart_start_rx_dma()
1413 sport->dma_rx_desc->callback_param = sport; in lpuart_start_rx_dma()
1414 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); in lpuart_start_rx_dma()
1418 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_start_rx_dma()
1420 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); in lpuart_start_rx_dma()
1422 if (sport->dma_idle_int) { in lpuart_start_rx_dma()
1423 unsigned long ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart_start_rx_dma()
1425 lpuart32_write(&sport->port, ctrl | UARTCTRL_ILIE, UARTCTRL); in lpuart_start_rx_dma()
1428 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, in lpuart_start_rx_dma()
1429 sport->port.membase + UARTCR5); in lpuart_start_rx_dma()
1439 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_dma_rx_free()
1442 if (!sport->dma_idle_int) in lpuart_dma_rx_free()
1443 del_timer_sync(&sport->lpuart_timer); in lpuart_dma_rx_free()
1445 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); in lpuart_dma_rx_free()
1446 kfree(sport->rx_ring.buf); in lpuart_dma_rx_free()
1447 sport->rx_ring.tail = 0; in lpuart_dma_rx_free()
1448 sport->rx_ring.head = 0; in lpuart_dma_rx_free()
1449 sport->dma_rx_desc = NULL; in lpuart_dma_rx_free()
1450 sport->dma_rx_cookie = -EINVAL; in lpuart_dma_rx_free()
1454 struct serial_rs485 *rs485) in lpuart_config_rs485() argument
1459 u8 modem = readb(sport->port.membase + UARTMODEM) & in lpuart_config_rs485()
1461 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1463 if (rs485->flags & SER_RS485_ENABLED) { in lpuart_config_rs485()
1464 /* Enable auto RS-485 RTS mode */ in lpuart_config_rs485()
1468 * The hardware defaults to RTS logic HIGH while transfer. in lpuart_config_rs485()
1469 * Switch polarity in case RTS shall be logic HIGH in lpuart_config_rs485()
1471 * Note: UART is assumed to be active high. in lpuart_config_rs485()
1473 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpuart_config_rs485()
1475 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart_config_rs485()
1479 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1484 struct serial_rs485 *rs485) in lpuart32_config_rs485() argument
1489 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) in lpuart32_config_rs485()
1491 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1493 if (rs485->flags & SER_RS485_ENABLED) { in lpuart32_config_rs485()
1494 /* Enable auto RS-485 RTS mode */ in lpuart32_config_rs485()
1498 * The hardware defaults to RTS logic HIGH while transfer. in lpuart32_config_rs485()
1499 * Switch polarity in case RTS shall be logic HIGH in lpuart32_config_rs485()
1501 * Note: UART is assumed to be active high. in lpuart32_config_rs485()
1503 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpuart32_config_rs485()
1505 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart32_config_rs485()
1509 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1518 reg = readb(port->membase + UARTCR1); in lpuart_get_mctrl()
1541 reg = readb(port->membase + UARTCR1); in lpuart_set_mctrl()
1548 writeb(reg, port->membase + UARTCR1); in lpuart_set_mctrl()
1569 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; in lpuart_break_ctl()
1574 writeb(temp, port->membase + UARTCR2); in lpuart_break_ctl()
1603 /* Disable the TXINV to turn off break and re-enable transmitter. */ in lpuart32_break_ctl()
1616 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1620 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1622 val = readb(sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1624 sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1628 sport->port.membase + UARTCFIFO); in lpuart_setup_watermark()
1631 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_setup_watermark()
1632 readb(sport->port.membase + UARTDR); in lpuart_setup_watermark()
1633 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_setup_watermark()
1636 if (uart_console(&sport->port)) in lpuart_setup_watermark()
1637 sport->rx_watermark = 1; in lpuart_setup_watermark()
1638 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_setup_watermark()
1639 writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO); in lpuart_setup_watermark()
1642 writeb(cr2_saved, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1651 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1653 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1661 ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark()
1665 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_setup_watermark()
1668 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_setup_watermark()
1672 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart32_setup_watermark()
1675 if (uart_console(&sport->port)) in lpuart32_setup_watermark()
1676 sport->rx_watermark = 1; in lpuart32_setup_watermark()
1677 val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) | in lpuart32_setup_watermark()
1679 lpuart32_write(&sport->port, val, UARTWATER); in lpuart32_setup_watermark()
1681 /* set RTS watermark */ in lpuart32_setup_watermark()
1682 if (!uart_console(&sport->port)) { in lpuart32_setup_watermark()
1683 val = lpuart32_read(&sport->port, UARTMODIR); in lpuart32_setup_watermark()
1684 val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1); in lpuart32_setup_watermark()
1685 lpuart32_write(&sport->port, val, UARTMODIR); in lpuart32_setup_watermark()
1689 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); in lpuart32_setup_watermark()
1698 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark_enable()
1701 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_setup_watermark_enable()
1706 if (sport->dma_idle_int) in rx_dma_timer_init()
1709 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); in rx_dma_timer_init()
1710 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; in rx_dma_timer_init()
1711 add_timer(&sport->lpuart_timer); in rx_dma_timer_init()
1716 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); in lpuart_request_dma()
1717 if (IS_ERR(sport->dma_tx_chan)) { in lpuart_request_dma()
1718 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1720 PTR_ERR(sport->dma_tx_chan)); in lpuart_request_dma()
1721 sport->dma_tx_chan = NULL; in lpuart_request_dma()
1724 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); in lpuart_request_dma()
1725 if (IS_ERR(sport->dma_rx_chan)) { in lpuart_request_dma()
1726 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1728 PTR_ERR(sport->dma_rx_chan)); in lpuart_request_dma()
1729 sport->dma_rx_chan = NULL; in lpuart_request_dma()
1738 if (uart_console(&sport->port)) in lpuart_tx_dma_startup()
1741 if (!sport->dma_tx_chan) in lpuart_tx_dma_startup()
1744 ret = lpuart_dma_tx_request(&sport->port); in lpuart_tx_dma_startup()
1748 init_waitqueue_head(&sport->dma_wait); in lpuart_tx_dma_startup()
1749 sport->lpuart_dma_tx_use = true; in lpuart_tx_dma_startup()
1751 uartbaud = lpuart32_read(&sport->port, UARTBAUD); in lpuart_tx_dma_startup()
1752 lpuart32_write(&sport->port, in lpuart_tx_dma_startup()
1755 writeb(readb(sport->port.membase + UARTCR5) | in lpuart_tx_dma_startup()
1756 UARTCR5_TDMAS, sport->port.membase + UARTCR5); in lpuart_tx_dma_startup()
1762 sport->lpuart_dma_tx_use = false; in lpuart_tx_dma_startup()
1770 if (uart_console(&sport->port)) in lpuart_rx_dma_startup()
1773 if (!sport->dma_rx_chan) in lpuart_rx_dma_startup()
1777 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); in lpuart_rx_dma_startup()
1783 if (!sport->dma_rx_timeout) in lpuart_rx_dma_startup()
1784 sport->dma_rx_timeout = 1; in lpuart_rx_dma_startup()
1786 sport->lpuart_dma_rx_use = true; in lpuart_rx_dma_startup()
1789 if (sport->port.has_sysrq && !lpuart_is_32(sport)) { in lpuart_rx_dma_startup()
1790 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1792 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1798 sport->lpuart_dma_rx_use = false; in lpuart_rx_dma_startup()
1805 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_hw_setup()
1812 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_hw_setup()
1821 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_startup()
1823 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & in lpuart_startup()
1825 sport->port.fifosize = sport->txfifo_size; in lpuart_startup()
1827 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & in lpuart_startup()
1840 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_hw_disable()
1843 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_hw_disable()
1850 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_configure()
1851 if (!sport->lpuart_dma_rx_use) in lpuart32_configure()
1853 if (!sport->lpuart_dma_tx_use) in lpuart32_configure()
1855 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_configure()
1862 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_hw_setup()
1872 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_hw_setup()
1881 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_startup()
1883 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & in lpuart32_startup()
1885 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1887 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & in lpuart32_startup()
1896 sport->rxfifo_size = 16; in lpuart32_startup()
1897 sport->txfifo_size = 16; in lpuart32_startup()
1898 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1909 if (sport->lpuart_dma_rx_use) { in lpuart_dma_shutdown()
1910 lpuart_dma_rx_free(&sport->port); in lpuart_dma_shutdown()
1911 sport->lpuart_dma_rx_use = false; in lpuart_dma_shutdown()
1914 if (sport->lpuart_dma_tx_use) { in lpuart_dma_shutdown()
1915 if (wait_event_interruptible_timeout(sport->dma_wait, in lpuart_dma_shutdown()
1916 !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) { in lpuart_dma_shutdown()
1917 sport->dma_tx_in_progress = false; in lpuart_dma_shutdown()
1918 dmaengine_terminate_sync(sport->dma_tx_chan); in lpuart_dma_shutdown()
1920 sport->lpuart_dma_tx_use = false; in lpuart_dma_shutdown()
1923 if (sport->dma_tx_chan) in lpuart_dma_shutdown()
1924 dma_release_channel(sport->dma_tx_chan); in lpuart_dma_shutdown()
1925 if (sport->dma_rx_chan) in lpuart_dma_shutdown()
1926 dma_release_channel(sport->dma_rx_chan); in lpuart_dma_shutdown()
1935 spin_lock_irqsave(&port->lock, flags); in lpuart_shutdown()
1938 temp = readb(port->membase + UARTCR2); in lpuart_shutdown()
1941 writeb(temp, port->membase + UARTCR2); in lpuart_shutdown()
1943 spin_unlock_irqrestore(&port->lock, flags); in lpuart_shutdown()
1955 spin_lock_irqsave(&port->lock, flags); in lpuart32_shutdown()
1958 temp = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_shutdown()
1959 lpuart32_write(&sport->port, temp, UARTSTAT); in lpuart32_shutdown()
1972 spin_unlock_irqrestore(&port->lock, flags); in lpuart32_shutdown()
1985 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in lpuart_set_termios()
1988 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); in lpuart_set_termios()
1989 old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_set_termios()
1990 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_set_termios()
1991 cr4 = readb(sport->port.membase + UARTCR4); in lpuart_set_termios()
1992 bdh = readb(sport->port.membase + UARTBDH); in lpuart_set_termios()
1993 modem = readb(sport->port.membase + UARTMODEM); in lpuart_set_termios()
1997 * - (7,e/o,1) in lpuart_set_termios()
1998 * - (8,n,1) in lpuart_set_termios()
1999 * - (8,m/s,1) in lpuart_set_termios()
2000 * - (8,e/o,1) in lpuart_set_termios()
2002 while ((termios->c_cflag & CSIZE) != CS8 && in lpuart_set_termios()
2003 (termios->c_cflag & CSIZE) != CS7) { in lpuart_set_termios()
2004 termios->c_cflag &= ~CSIZE; in lpuart_set_termios()
2005 termios->c_cflag |= old_csize; in lpuart_set_termios()
2009 if ((termios->c_cflag & CSIZE) == CS8 || in lpuart_set_termios()
2010 (termios->c_cflag & CSIZE) == CS7) in lpuart_set_termios()
2013 if (termios->c_cflag & CMSPAR) { in lpuart_set_termios()
2014 if ((termios->c_cflag & CSIZE) != CS8) { in lpuart_set_termios()
2015 termios->c_cflag &= ~CSIZE; in lpuart_set_termios()
2016 termios->c_cflag |= CS8; in lpuart_set_termios()
2022 * When auto RS-485 RTS mode is enabled, in lpuart_set_termios()
2025 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart_set_termios()
2026 termios->c_cflag &= ~CRTSCTS; in lpuart_set_termios()
2028 if (termios->c_cflag & CRTSCTS) in lpuart_set_termios()
2033 termios->c_cflag &= ~CSTOPB; in lpuart_set_termios()
2035 /* parity must be enabled when CS7 to match 8-bits format */ in lpuart_set_termios()
2036 if ((termios->c_cflag & CSIZE) == CS7) in lpuart_set_termios()
2037 termios->c_cflag |= PARENB; in lpuart_set_termios()
2039 if (termios->c_cflag & PARENB) { in lpuart_set_termios()
2040 if (termios->c_cflag & CMSPAR) { in lpuart_set_termios()
2042 if (termios->c_cflag & PARODD) in lpuart_set_termios()
2048 if ((termios->c_cflag & CSIZE) == CS8) in lpuart_set_termios()
2050 if (termios->c_cflag & PARODD) in lpuart_set_termios()
2060 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in lpuart_set_termios()
2066 * Since timer function acqures sport->port.lock, need to stop before in lpuart_set_termios()
2069 if (old && sport->lpuart_dma_rx_use) in lpuart_set_termios()
2070 lpuart_dma_rx_free(&sport->port); in lpuart_set_termios()
2072 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_set_termios()
2074 sport->port.read_status_mask = 0; in lpuart_set_termios()
2075 if (termios->c_iflag & INPCK) in lpuart_set_termios()
2076 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; in lpuart_set_termios()
2077 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in lpuart_set_termios()
2078 sport->port.read_status_mask |= UARTSR1_FE; in lpuart_set_termios()
2081 sport->port.ignore_status_mask = 0; in lpuart_set_termios()
2082 if (termios->c_iflag & IGNPAR) in lpuart_set_termios()
2083 sport->port.ignore_status_mask |= UARTSR1_PE; in lpuart_set_termios()
2084 if (termios->c_iflag & IGNBRK) { in lpuart_set_termios()
2085 sport->port.ignore_status_mask |= UARTSR1_FE; in lpuart_set_termios()
2090 if (termios->c_iflag & IGNPAR) in lpuart_set_termios()
2091 sport->port.ignore_status_mask |= UARTSR1_OR; in lpuart_set_termios()
2094 /* update the per-port timeout */ in lpuart_set_termios()
2095 uart_update_timeout(port, termios->c_cflag, baud); in lpuart_set_termios()
2098 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_set_termios()
2102 sport->port.membase + UARTCR2); in lpuart_set_termios()
2104 sbr = sport->port.uartclk / (16 * baud); in lpuart_set_termios()
2105 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; in lpuart_set_termios()
2110 writeb(cr4 | brfa, sport->port.membase + UARTCR4); in lpuart_set_termios()
2111 writeb(bdh, sport->port.membase + UARTBDH); in lpuart_set_termios()
2112 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); in lpuart_set_termios()
2113 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_set_termios()
2114 writeb(cr1, sport->port.membase + UARTCR1); in lpuart_set_termios()
2115 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_set_termios()
2118 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_set_termios()
2120 if (old && sport->lpuart_dma_rx_use) { in lpuart_set_termios()
2124 sport->lpuart_dma_rx_use = false; in lpuart_set_termios()
2127 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_set_termios()
2135 u32 clk = port->uartclk; in __lpuart32_serial_setbrg()
2138 * The idea is to use the best OSR (over-sampling rate) possible. in __lpuart32_serial_setbrg()
2139 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. in __lpuart32_serial_setbrg()
2160 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; in __lpuart32_serial_setbrg()
2164 if (tmp_diff > (baudrate - tmp)) { in __lpuart32_serial_setbrg()
2165 tmp_diff = baudrate - tmp; in __lpuart32_serial_setbrg()
2184 dev_warn(port->dev, in __lpuart32_serial_setbrg()
2193 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; in __lpuart32_serial_setbrg()
2209 __lpuart32_serial_setbrg(&sport->port, baudrate, in lpuart32_serial_setbrg()
2210 sport->lpuart_dma_rx_use, in lpuart32_serial_setbrg()
2211 sport->lpuart_dma_tx_use); in lpuart32_serial_setbrg()
2223 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in lpuart32_set_termios()
2225 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_set_termios()
2226 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart32_set_termios()
2227 modem = lpuart32_read(&sport->port, UARTMODIR); in lpuart32_set_termios()
2228 sport->is_cs7 = false; in lpuart32_set_termios()
2232 * - (7,e/o,1) in lpuart32_set_termios()
2233 * - (8,n,1) in lpuart32_set_termios()
2234 * - (8,m/s,1) in lpuart32_set_termios()
2235 * - (8,e/o,1) in lpuart32_set_termios()
2237 while ((termios->c_cflag & CSIZE) != CS8 && in lpuart32_set_termios()
2238 (termios->c_cflag & CSIZE) != CS7) { in lpuart32_set_termios()
2239 termios->c_cflag &= ~CSIZE; in lpuart32_set_termios()
2240 termios->c_cflag |= old_csize; in lpuart32_set_termios()
2244 if ((termios->c_cflag & CSIZE) == CS8 || in lpuart32_set_termios()
2245 (termios->c_cflag & CSIZE) == CS7) in lpuart32_set_termios()
2248 if (termios->c_cflag & CMSPAR) { in lpuart32_set_termios()
2249 if ((termios->c_cflag & CSIZE) != CS8) { in lpuart32_set_termios()
2250 termios->c_cflag &= ~CSIZE; in lpuart32_set_termios()
2251 termios->c_cflag |= CS8; in lpuart32_set_termios()
2257 * When auto RS-485 RTS mode is enabled, in lpuart32_set_termios()
2260 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart32_set_termios()
2261 termios->c_cflag &= ~CRTSCTS; in lpuart32_set_termios()
2263 if (termios->c_cflag & CRTSCTS) in lpuart32_set_termios()
2268 if (termios->c_cflag & CSTOPB) in lpuart32_set_termios()
2273 /* parity must be enabled when CS7 to match 8-bits format */ in lpuart32_set_termios()
2274 if ((termios->c_cflag & CSIZE) == CS7) in lpuart32_set_termios()
2275 termios->c_cflag |= PARENB; in lpuart32_set_termios()
2277 if ((termios->c_cflag & PARENB)) { in lpuart32_set_termios()
2278 if (termios->c_cflag & CMSPAR) { in lpuart32_set_termios()
2283 if ((termios->c_cflag & CSIZE) == CS8) in lpuart32_set_termios()
2285 if (termios->c_cflag & PARODD) in lpuart32_set_termios()
2295 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); in lpuart32_set_termios()
2301 * Since timer function acqures sport->port.lock, need to stop before in lpuart32_set_termios()
2304 if (old && sport->lpuart_dma_rx_use) in lpuart32_set_termios()
2305 lpuart_dma_rx_free(&sport->port); in lpuart32_set_termios()
2307 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_set_termios()
2309 sport->port.read_status_mask = 0; in lpuart32_set_termios()
2310 if (termios->c_iflag & INPCK) in lpuart32_set_termios()
2311 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; in lpuart32_set_termios()
2312 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in lpuart32_set_termios()
2313 sport->port.read_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2316 sport->port.ignore_status_mask = 0; in lpuart32_set_termios()
2317 if (termios->c_iflag & IGNPAR) in lpuart32_set_termios()
2318 sport->port.ignore_status_mask |= UARTSTAT_PE; in lpuart32_set_termios()
2319 if (termios->c_iflag & IGNBRK) { in lpuart32_set_termios()
2320 sport->port.ignore_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2325 if (termios->c_iflag & IGNPAR) in lpuart32_set_termios()
2326 sport->port.ignore_status_mask |= UARTSTAT_OR; in lpuart32_set_termios()
2329 /* update the per-port timeout */ in lpuart32_set_termios()
2330 uart_update_timeout(port, termios->c_cflag, baud); in lpuart32_set_termios()
2338 lpuart32_write(&sport->port, 0, UARTMODIR); in lpuart32_set_termios()
2339 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_set_termios()
2343 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), in lpuart32_set_termios()
2346 lpuart32_write(&sport->port, bd, UARTBAUD); in lpuart32_set_termios()
2349 lpuart32_write(&sport->port, modem & ~UARTMODIR_TXCTSE, UARTMODIR); in lpuart32_set_termios()
2351 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_set_termios()
2352 /* re-enable the CTS if needed */ in lpuart32_set_termios()
2353 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_set_termios()
2356 sport->is_cs7 = true; in lpuart32_set_termios()
2358 if (old && sport->lpuart_dma_rx_use) { in lpuart32_set_termios()
2362 sport->lpuart_dma_rx_use = false; in lpuart32_set_termios()
2365 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_set_termios()
2387 port->type = PORT_LPUART; in lpuart_config_port()
2394 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) in lpuart_verify_port()
2395 ret = -EINVAL; in lpuart_verify_port()
2396 if (port->irq != ser->irq) in lpuart_verify_port()
2397 ret = -EINVAL; in lpuart_verify_port()
2398 if (ser->io_type != UPIO_MEM) in lpuart_verify_port()
2399 ret = -EINVAL; in lpuart_verify_port()
2400 if (port->uartclk / 16 != ser->baud_base) in lpuart_verify_port()
2401 ret = -EINVAL; in lpuart_verify_port()
2402 if (port->iobase != ser->port) in lpuart_verify_port()
2403 ret = -EINVAL; in lpuart_verify_port()
2404 if (ser->hub6 != 0) in lpuart_verify_port()
2405 ret = -EINVAL; in lpuart_verify_port()
2465 writeb(ch, port->membase + UARTDR); in lpuart_console_putchar()
2477 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart_console_write()
2483 locked = spin_trylock_irqsave(&sport->port.lock, flags); in lpuart_console_write()
2485 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_console_write()
2488 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_console_write()
2491 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2493 uart_console_write(&sport->port, s, count, lpuart_console_putchar); in lpuart_console_write()
2496 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_console_write()
2498 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2501 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_console_write()
2507 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart32_console_write()
2513 locked = spin_trylock_irqsave(&sport->port.lock, flags); in lpuart32_console_write()
2515 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_console_write()
2518 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_write()
2521 lpuart32_write(&sport->port, cr, UARTCTRL); in lpuart32_console_write()
2523 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); in lpuart32_console_write()
2526 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_console_write()
2528 lpuart32_write(&sport->port, old_cr, UARTCTRL); in lpuart32_console_write()
2531 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_console_write()
2545 cr = readb(sport->port.membase + UARTCR2); in lpuart_console_get_options()
2552 cr = readb(sport->port.membase + UARTCR1); in lpuart_console_get_options()
2567 bdh = readb(sport->port.membase + UARTBDH); in lpuart_console_get_options()
2569 bdl = readb(sport->port.membase + UARTBDL); in lpuart_console_get_options()
2573 brfa = readb(sport->port.membase + UARTCR4); in lpuart_console_get_options()
2583 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart_console_get_options()
2594 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2601 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2616 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart32_console_get_options()
2629 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart32_console_get_options()
2646 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) in lpuart_console_setup()
2647 co->index = 0; in lpuart_console_setup()
2649 sport = lpuart_ports[co->index]; in lpuart_console_setup()
2651 return -ENODEV; in lpuart_console_setup()
2666 return uart_set_options(&sport->port, co, baud, parity, bits, flow); in lpuart_console_setup()
2676 .index = -1,
2686 .index = -1,
2692 struct earlycon_device *dev = con->data; in lpuart_early_write()
2694 uart_console_write(&dev->port, s, n, lpuart_console_putchar); in lpuart_early_write()
2699 struct earlycon_device *dev = con->data; in lpuart32_early_write()
2701 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); in lpuart32_early_write()
2707 if (!device->port.membase) in lpuart_early_console_setup()
2708 return -ENODEV; in lpuart_early_console_setup()
2710 device->con->write = lpuart_early_write; in lpuart_early_console_setup()
2717 if (!device->port.membase) in lpuart32_early_console_setup()
2718 return -ENODEV; in lpuart32_early_console_setup()
2720 if (device->port.iotype != UPIO_MEM32) in lpuart32_early_console_setup()
2721 device->port.iotype = UPIO_MEM32BE; in lpuart32_early_console_setup()
2723 device->con->write = lpuart32_early_write; in lpuart32_early_console_setup()
2732 if (!device->port.membase) in ls1028a_early_console_setup()
2733 return -ENODEV; in ls1028a_early_console_setup()
2735 device->port.iotype = UPIO_MEM32; in ls1028a_early_console_setup()
2736 device->con->write = lpuart32_early_write; in ls1028a_early_console_setup()
2739 if (device->port.uartclk && device->baud) in ls1028a_early_console_setup()
2740 __lpuart32_serial_setbrg(&device->port, device->baud, in ls1028a_early_console_setup()
2744 cr = lpuart32_read(&device->port, UARTCTRL); in ls1028a_early_console_setup()
2746 lpuart32_write(&device->port, cr, UARTCTRL); in ls1028a_early_console_setup()
2754 if (!device->port.membase) in lpuart32_imx_early_console_setup()
2755 return -ENODEV; in lpuart32_imx_early_console_setup()
2757 device->port.iotype = UPIO_MEM32; in lpuart32_imx_early_console_setup()
2758 device->port.membase += IMX_REG_OFF; in lpuart32_imx_early_console_setup()
2759 device->con->write = lpuart32_early_write; in lpuart32_imx_early_console_setup()
2763 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2764 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2765 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2766 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2767 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup);
2768 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2769 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup);
2795 struct uart_port *port = &sport->port; in lpuart_global_reset()
2801 ret = clk_prepare_enable(sport->ipg_clk); in lpuart_global_reset()
2803 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret); in lpuart_global_reset()
2814 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart_global_reset()
2817 dev_warn(sport->port.dev, in lpuart_global_reset()
2819 clk_disable_unprepare(sport->ipg_clk); in lpuart_global_reset()
2824 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF; in lpuart_global_reset()
2837 clk_disable_unprepare(sport->ipg_clk); in lpuart_global_reset()
2843 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev); in lpuart_probe()
2844 struct device_node *np = pdev->dev.of_node; in lpuart_probe()
2850 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in lpuart_probe()
2852 return -ENOMEM; in lpuart_probe()
2854 sport->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in lpuart_probe()
2855 if (IS_ERR(sport->port.membase)) in lpuart_probe()
2856 return PTR_ERR(sport->port.membase); in lpuart_probe()
2858 sport->port.membase += sdata->reg_off; in lpuart_probe()
2859 sport->port.mapbase = res->start + sdata->reg_off; in lpuart_probe()
2860 sport->port.dev = &pdev->dev; in lpuart_probe()
2861 sport->port.type = PORT_LPUART; in lpuart_probe()
2862 sport->devtype = sdata->devtype; in lpuart_probe()
2863 sport->rx_watermark = sdata->rx_watermark; in lpuart_probe()
2864 sport->dma_idle_int = is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || in lpuart_probe()
2869 sport->port.irq = ret; in lpuart_probe()
2870 sport->port.iotype = sdata->iotype; in lpuart_probe()
2872 sport->port.ops = &lpuart32_pops; in lpuart_probe()
2874 sport->port.ops = &lpuart_pops; in lpuart_probe()
2875 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); in lpuart_probe()
2876 sport->port.flags = UPF_BOOT_AUTOCONF; in lpuart_probe()
2879 sport->port.rs485_config = lpuart32_config_rs485; in lpuart_probe()
2881 sport->port.rs485_config = lpuart_config_rs485; in lpuart_probe()
2882 sport->port.rs485_supported = lpuart_rs485_supported; in lpuart_probe()
2884 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); in lpuart_probe()
2885 if (IS_ERR(sport->ipg_clk)) { in lpuart_probe()
2886 ret = PTR_ERR(sport->ipg_clk); in lpuart_probe()
2887 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); in lpuart_probe()
2891 sport->baud_clk = NULL; in lpuart_probe()
2893 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); in lpuart_probe()
2894 if (IS_ERR(sport->baud_clk)) { in lpuart_probe()
2895 ret = PTR_ERR(sport->baud_clk); in lpuart_probe()
2896 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); in lpuart_probe()
2903 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in lpuart_probe()
2907 dev_err(&pdev->dev, "serial%d out of range\n", ret); in lpuart_probe()
2908 return -EINVAL; in lpuart_probe()
2910 sport->port.line = ret; in lpuart_probe()
2915 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); in lpuart_probe()
2917 lpuart_ports[sport->port.line] = sport; in lpuart_probe()
2919 platform_set_drvdata(pdev, &sport->port); in lpuart_probe()
2929 pm_runtime_use_autosuspend(&pdev->dev); in lpuart_probe()
2930 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); in lpuart_probe()
2931 pm_runtime_set_active(&pdev->dev); in lpuart_probe()
2932 pm_runtime_enable(&pdev->dev); in lpuart_probe()
2933 pm_runtime_mark_last_busy(&pdev->dev); in lpuart_probe()
2939 ret = uart_get_rs485_mode(&sport->port); in lpuart_probe()
2943 ret = uart_add_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2947 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0, in lpuart_probe()
2955 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2959 pm_runtime_disable(&pdev->dev); in lpuart_probe()
2960 pm_runtime_set_suspended(&pdev->dev); in lpuart_probe()
2961 pm_runtime_dont_use_autosuspend(&pdev->dev); in lpuart_probe()
2970 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_remove()
2974 if (sport->dma_tx_chan) in lpuart_remove()
2975 dma_release_channel(sport->dma_tx_chan); in lpuart_remove()
2977 if (sport->dma_rx_chan) in lpuart_remove()
2978 dma_release_channel(sport->dma_rx_chan); in lpuart_remove()
2980 pm_runtime_disable(&pdev->dev); in lpuart_remove()
2981 pm_runtime_set_suspended(&pdev->dev); in lpuart_remove()
2982 pm_runtime_dont_use_autosuspend(&pdev->dev); in lpuart_remove()
3009 val = lpuart32_read(&sport->port, UARTCTRL); in serial_lpuart_enable_wakeup()
3010 baud = lpuart32_read(&sport->port, UARTBAUD); in serial_lpuart_enable_wakeup()
3013 lpuart32_write(&sport->port, 0, UARTWATER); in serial_lpuart_enable_wakeup()
3016 lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT); in serial_lpuart_enable_wakeup()
3022 lpuart32_write(&sport->port, val, UARTCTRL); in serial_lpuart_enable_wakeup()
3023 lpuart32_write(&sport->port, baud, UARTBAUD); in serial_lpuart_enable_wakeup()
3025 val = readb(sport->port.membase + UARTCR2); in serial_lpuart_enable_wakeup()
3030 writeb(val, sport->port.membase + UARTCR2); in serial_lpuart_enable_wakeup()
3036 struct tty_port *port = &sport->port.state->port; in lpuart_uport_is_active()
3043 tty_dev = tty->dev; in lpuart_uport_is_active()
3049 (!console_suspend_enabled && uart_console(&sport->port))) in lpuart_uport_is_active()
3058 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); in lpuart_suspend_noirq()
3080 val = lpuart32_read(&sport->port, UARTSTAT); in lpuart_resume_noirq()
3081 lpuart32_write(&sport->port, val, UARTSTAT); in lpuart_resume_noirq()
3093 uart_suspend_port(&lpuart_reg, &sport->port); in lpuart_suspend()
3096 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_suspend()
3099 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart_suspend()
3101 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart_suspend()
3104 temp = readb(sport->port.membase + UARTCR2); in lpuart_suspend()
3106 writeb(temp, sport->port.membase + UARTCR2); in lpuart_suspend()
3108 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_suspend()
3110 if (sport->lpuart_dma_rx_use) { in lpuart_suspend()
3113 * non-idle DMA channels. If port wakeup is enabled or if port in lpuart_suspend()
3118 lpuart_dma_rx_free(&sport->port); in lpuart_suspend()
3121 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_suspend()
3123 temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_suspend()
3124 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, in lpuart_suspend()
3127 writeb(readb(sport->port.membase + UARTCR5) & in lpuart_suspend()
3128 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); in lpuart_suspend()
3130 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_suspend()
3133 if (sport->lpuart_dma_tx_use) { in lpuart_suspend()
3134 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_suspend()
3136 temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_suspend()
3138 lpuart32_write(&sport->port, temp, UARTBAUD); in lpuart_suspend()
3140 temp = readb(sport->port.membase + UARTCR5); in lpuart_suspend()
3142 writeb(temp, sport->port.membase + UARTCR5); in lpuart_suspend()
3144 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_suspend()
3145 sport->dma_tx_in_progress = false; in lpuart_suspend()
3146 dmaengine_terminate_sync(sport->dma_tx_chan); in lpuart_suspend()
3148 } else if (pm_runtime_active(sport->port.dev)) { in lpuart_suspend()
3150 pm_runtime_disable(sport->port.dev); in lpuart_suspend()
3151 pm_runtime_set_suspended(sport->port.dev); in lpuart_suspend()
3159 struct tty_port *port = &sport->port.state->port; in lpuart_console_fixup()
3160 struct uart_port *uport = &sport->port; in lpuart_console_fixup()
3171 console_suspend_enabled && uart_console(&sport->port)) { in lpuart_console_fixup()
3173 mutex_lock(&port->mutex); in lpuart_console_fixup()
3175 termios.c_cflag = uport->cons->cflag; in lpuart_console_fixup()
3176 if (port->tty && termios.c_cflag == 0) in lpuart_console_fixup()
3177 termios = port->tty->termios; in lpuart_console_fixup()
3178 uport->ops->set_termios(uport, &termios, NULL); in lpuart_console_fixup()
3179 mutex_unlock(&port->mutex); in lpuart_console_fixup()
3193 } else if (pm_runtime_active(sport->port.dev)) { in lpuart_resume()
3197 pm_runtime_set_active(sport->port.dev); in lpuart_resume()
3198 pm_runtime_enable(sport->port.dev); in lpuart_resume()
3202 uart_resume_port(&lpuart_reg, &sport->port); in lpuart_resume()
3219 .name = "fsl-lpuart",