Lines Matching +full:tx +full:- +full:clk +full:- +full:100 +full:- +full:inverted
1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2010 ST-Ericsson SA
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
32 #include <linux/clk.h>
35 #include <linux/dma-mapping.h>
82 /* The size of the array - must be last */
257 struct clk *clk; member
262 unsigned int fifosize; /* vendor-specific */
263 unsigned int fixed_baud; /* vendor-set fixed baud rate */
282 return uap->reg_offset[reg]; in pl011_reg_to_offset()
288 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); in pl011_read()
290 return (uap->port.iotype == UPIO_MEM32) ? in pl011_read()
297 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); in pl011_write()
299 if (uap->port.iotype == UPIO_MEM32) in pl011_write()
325 uap->port.icount.rx++; in pl011_fifo_to_tty()
330 uap->port.icount.brk++; in pl011_fifo_to_tty()
331 if (uart_handle_break(&uap->port)) in pl011_fifo_to_tty()
334 uap->port.icount.parity++; in pl011_fifo_to_tty()
336 uap->port.icount.frame++; in pl011_fifo_to_tty()
338 uap->port.icount.overrun++; in pl011_fifo_to_tty()
340 ch &= uap->port.read_status_mask; in pl011_fifo_to_tty()
350 uart_port_unlock(&uap->port); in pl011_fifo_to_tty()
351 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255); in pl011_fifo_to_tty()
352 uart_port_lock(&uap->port); in pl011_fifo_to_tty()
355 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); in pl011_fifo_to_tty()
374 db->buf = dma_alloc_coherent(chan->device->dev, PL011_DMA_BUFFER_SIZE, in pl011_dmabuf_init()
375 &db->dma, GFP_KERNEL); in pl011_dmabuf_init()
376 if (!db->buf) in pl011_dmabuf_init()
377 return -ENOMEM; in pl011_dmabuf_init()
378 db->len = PL011_DMA_BUFFER_SIZE; in pl011_dmabuf_init()
386 if (db->buf) { in pl011_dmabuf_free()
387 dma_free_coherent(chan->device->dev, in pl011_dmabuf_free()
388 PL011_DMA_BUFFER_SIZE, db->buf, db->dma); in pl011_dmabuf_free()
395 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); in pl011_dma_probe()
396 struct device *dev = uap->port.dev; in pl011_dma_probe()
398 .dst_addr = uap->port.mapbase + in pl011_dma_probe()
402 .dst_maxburst = uap->fifosize >> 1, in pl011_dma_probe()
408 uap->dma_probed = true; in pl011_dma_probe()
409 chan = dma_request_chan(dev, "tx"); in pl011_dma_probe()
411 if (PTR_ERR(chan) == -EPROBE_DEFER) { in pl011_dma_probe()
412 uap->dma_probed = false; in pl011_dma_probe()
417 if (!plat || !plat->dma_filter) { in pl011_dma_probe()
418 dev_info(uap->port.dev, "no DMA platform data\n"); in pl011_dma_probe()
422 /* Try to acquire a generic DMA engine slave TX channel */ in pl011_dma_probe()
426 chan = dma_request_channel(mask, plat->dma_filter, in pl011_dma_probe()
427 plat->dma_tx_param); in pl011_dma_probe()
429 dev_err(uap->port.dev, "no TX DMA channel!\n"); in pl011_dma_probe()
435 uap->dmatx.chan = chan; in pl011_dma_probe()
437 dev_info(uap->port.dev, "DMA channel TX %s\n", in pl011_dma_probe()
438 dma_chan_name(uap->dmatx.chan)); in pl011_dma_probe()
443 if (!chan && plat && plat->dma_rx_param) { in pl011_dma_probe()
444 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); in pl011_dma_probe()
447 dev_err(uap->port.dev, "no RX DMA channel!\n"); in pl011_dma_probe()
454 .src_addr = uap->port.mapbase + in pl011_dma_probe()
458 .src_maxburst = uap->fifosize >> 2, in pl011_dma_probe()
472 dev_info(uap->port.dev, in pl011_dma_probe()
473 "RX DMA disabled - no residue processing\n"); in pl011_dma_probe()
478 uap->dmarx.chan = chan; in pl011_dma_probe()
480 uap->dmarx.auto_poll_rate = false; in pl011_dma_probe()
481 if (plat && plat->dma_rx_poll_enable) { in pl011_dma_probe()
483 if (plat->dma_rx_poll_rate) { in pl011_dma_probe()
484 uap->dmarx.auto_poll_rate = false; in pl011_dma_probe()
485 uap->dmarx.poll_rate = plat->dma_rx_poll_rate; in pl011_dma_probe()
488 * 100 ms defaults to poll rate if not in pl011_dma_probe()
492 uap->dmarx.auto_poll_rate = true; in pl011_dma_probe()
493 uap->dmarx.poll_rate = 100; in pl011_dma_probe()
496 if (plat->dma_rx_poll_timeout) in pl011_dma_probe()
497 uap->dmarx.poll_timeout = in pl011_dma_probe()
498 plat->dma_rx_poll_timeout; in pl011_dma_probe()
500 uap->dmarx.poll_timeout = 3000; in pl011_dma_probe()
501 } else if (!plat && dev->of_node) { in pl011_dma_probe()
502 uap->dmarx.auto_poll_rate = of_property_read_bool( in pl011_dma_probe()
503 dev->of_node, "auto-poll"); in pl011_dma_probe()
504 if (uap->dmarx.auto_poll_rate) { in pl011_dma_probe()
507 if (0 == of_property_read_u32(dev->of_node, in pl011_dma_probe()
508 "poll-rate-ms", &x)) in pl011_dma_probe()
509 uap->dmarx.poll_rate = x; in pl011_dma_probe()
511 uap->dmarx.poll_rate = 100; in pl011_dma_probe()
512 if (0 == of_property_read_u32(dev->of_node, in pl011_dma_probe()
513 "poll-timeout-ms", &x)) in pl011_dma_probe()
514 uap->dmarx.poll_timeout = x; in pl011_dma_probe()
516 uap->dmarx.poll_timeout = 3000; in pl011_dma_probe()
519 dev_info(uap->port.dev, "DMA channel RX %s\n", in pl011_dma_probe()
520 dma_chan_name(uap->dmarx.chan)); in pl011_dma_probe()
526 if (uap->dmatx.chan) in pl011_dma_remove()
527 dma_release_channel(uap->dmatx.chan); in pl011_dma_remove()
528 if (uap->dmarx.chan) in pl011_dma_remove()
529 dma_release_channel(uap->dmarx.chan); in pl011_dma_remove()
537 * The current DMA TX buffer has been sent.
543 struct pl011_dmatx_data *dmatx = &uap->dmatx; in pl011_dma_tx_callback()
547 uart_port_lock_irqsave(&uap->port, &flags); in pl011_dma_tx_callback()
548 if (uap->dmatx.queued) in pl011_dma_tx_callback()
549 dma_unmap_single(dmatx->chan->device->dev, dmatx->dma, in pl011_dma_tx_callback()
550 dmatx->len, DMA_TO_DEVICE); in pl011_dma_tx_callback()
552 dmacr = uap->dmacr; in pl011_dma_tx_callback()
553 uap->dmacr = dmacr & ~UART011_TXDMAE; in pl011_dma_tx_callback()
554 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_callback()
557 * If TX DMA was disabled, it means that we've stopped the DMA for in pl011_dma_tx_callback()
558 * some reason (eg, XOFF received, or we want to send an X-char.) in pl011_dma_tx_callback()
561 * and the rest of the driver - if the driver disables TX DMA while in pl011_dma_tx_callback()
562 * a TX buffer completing, we must update the tx queued status to in pl011_dma_tx_callback()
565 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || in pl011_dma_tx_callback()
566 uart_circ_empty(&uap->port.state->xmit)) { in pl011_dma_tx_callback()
567 uap->dmatx.queued = false; in pl011_dma_tx_callback()
568 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_dma_tx_callback()
575 * have data pending to be sent. Re-enable the TX IRQ. in pl011_dma_tx_callback()
579 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_dma_tx_callback()
583 * Try to refill the TX DMA buffer.
586 * 1 if we queued up a TX DMA buffer.
592 struct pl011_dmatx_data *dmatx = &uap->dmatx; in pl011_dma_tx_refill()
593 struct dma_chan *chan = dmatx->chan; in pl011_dma_tx_refill()
594 struct dma_device *dma_dev = chan->device; in pl011_dma_tx_refill()
596 struct circ_buf *xmit = &uap->port.state->xmit; in pl011_dma_tx_refill()
606 if (count < (uap->fifosize >> 1)) { in pl011_dma_tx_refill()
607 uap->dmatx.queued = false; in pl011_dma_tx_refill()
615 count -= 1; in pl011_dma_tx_refill()
617 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ in pl011_dma_tx_refill()
621 if (xmit->tail < xmit->head) in pl011_dma_tx_refill()
622 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); in pl011_dma_tx_refill()
624 size_t first = UART_XMIT_SIZE - xmit->tail; in pl011_dma_tx_refill()
629 second = count - first; in pl011_dma_tx_refill()
631 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); in pl011_dma_tx_refill()
633 memcpy(&dmatx->buf[first], &xmit->buf[0], second); in pl011_dma_tx_refill()
636 dmatx->len = count; in pl011_dma_tx_refill()
637 dmatx->dma = dma_map_single(dma_dev->dev, dmatx->buf, count, in pl011_dma_tx_refill()
639 if (dmatx->dma == DMA_MAPPING_ERROR) { in pl011_dma_tx_refill()
640 uap->dmatx.queued = false; in pl011_dma_tx_refill()
641 dev_dbg(uap->port.dev, "unable to map TX DMA\n"); in pl011_dma_tx_refill()
642 return -EBUSY; in pl011_dma_tx_refill()
645 desc = dmaengine_prep_slave_single(chan, dmatx->dma, dmatx->len, DMA_MEM_TO_DEV, in pl011_dma_tx_refill()
648 dma_unmap_single(dma_dev->dev, dmatx->dma, dmatx->len, DMA_TO_DEVICE); in pl011_dma_tx_refill()
649 uap->dmatx.queued = false; in pl011_dma_tx_refill()
654 dev_dbg(uap->port.dev, "TX DMA busy\n"); in pl011_dma_tx_refill()
655 return -EBUSY; in pl011_dma_tx_refill()
659 desc->callback = pl011_dma_tx_callback; in pl011_dma_tx_refill()
660 desc->callback_param = uap; in pl011_dma_tx_refill()
666 dma_dev->device_issue_pending(chan); in pl011_dma_tx_refill()
668 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_refill()
669 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_refill()
670 uap->dmatx.queued = true; in pl011_dma_tx_refill()
676 uart_xmit_advance(&uap->port, count); in pl011_dma_tx_refill()
679 uart_write_wakeup(&uap->port); in pl011_dma_tx_refill()
685 * We received a transmit interrupt without a pending X-char but with
694 if (!uap->using_tx_dma) in pl011_dma_tx_irq()
698 * If we already have a TX buffer queued, but received a in pl011_dma_tx_irq()
699 * TX interrupt, it will be because we've just sent an X-char. in pl011_dma_tx_irq()
700 * Ensure the TX DMA is enabled and the TX IRQ is disabled. in pl011_dma_tx_irq()
702 if (uap->dmatx.queued) { in pl011_dma_tx_irq()
703 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_irq()
704 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_irq()
705 uap->im &= ~UART011_TXIM; in pl011_dma_tx_irq()
706 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_irq()
711 * We don't have a TX buffer queued, so try to queue one. in pl011_dma_tx_irq()
712 * If we successfully queued a buffer, mask the TX IRQ. in pl011_dma_tx_irq()
715 uap->im &= ~UART011_TXIM; in pl011_dma_tx_irq()
716 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_irq()
728 if (uap->dmatx.queued) { in pl011_dma_tx_stop()
729 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_tx_stop()
730 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_stop()
739 * false if we want the TX IRQ to be enabled
746 if (!uap->using_tx_dma) in pl011_dma_tx_start()
749 if (!uap->port.x_char) { in pl011_dma_tx_start()
750 /* no X-char, try to push chars out in DMA mode */ in pl011_dma_tx_start()
753 if (!uap->dmatx.queued) { in pl011_dma_tx_start()
755 uap->im &= ~UART011_TXIM; in pl011_dma_tx_start()
756 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_tx_start()
759 } else if (!(uap->dmacr & UART011_TXDMAE)) { in pl011_dma_tx_start()
760 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_start()
761 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_start()
767 * We have an X-char to send. Disable DMA to prevent it loading in pl011_dma_tx_start()
768 * the TX fifo, and then see if we can stuff it into the FIFO. in pl011_dma_tx_start()
770 dmacr = uap->dmacr; in pl011_dma_tx_start()
771 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_tx_start()
772 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_start()
778 * loaded the character, we should just re-enable DMA. in pl011_dma_tx_start()
783 pl011_write(uap->port.x_char, uap, REG_DR); in pl011_dma_tx_start()
784 uap->port.icount.tx++; in pl011_dma_tx_start()
785 uap->port.x_char = 0; in pl011_dma_tx_start()
787 /* Success - restore the DMA state */ in pl011_dma_tx_start()
788 uap->dmacr = dmacr; in pl011_dma_tx_start()
799 __releases(&uap->port.lock) in pl011_dma_flush_buffer()
800 __acquires(&uap->port.lock) in pl011_dma_flush_buffer()
805 if (!uap->using_tx_dma) in pl011_dma_flush_buffer()
808 dmaengine_terminate_async(uap->dmatx.chan); in pl011_dma_flush_buffer()
810 if (uap->dmatx.queued) { in pl011_dma_flush_buffer()
811 dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma, in pl011_dma_flush_buffer()
812 uap->dmatx.len, DMA_TO_DEVICE); in pl011_dma_flush_buffer()
813 uap->dmatx.queued = false; in pl011_dma_flush_buffer()
814 uap->dmacr &= ~UART011_TXDMAE; in pl011_dma_flush_buffer()
815 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_flush_buffer()
823 struct dma_chan *rxchan = uap->dmarx.chan; in pl011_dma_rx_trigger_dma()
824 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_trigger_dma()
829 return -EIO; in pl011_dma_rx_trigger_dma()
832 dbuf = uap->dmarx.use_buf_b ? in pl011_dma_rx_trigger_dma()
833 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; in pl011_dma_rx_trigger_dma()
834 desc = dmaengine_prep_slave_single(rxchan, dbuf->dma, dbuf->len, in pl011_dma_rx_trigger_dma()
843 uap->dmarx.running = false; in pl011_dma_rx_trigger_dma()
845 return -EBUSY; in pl011_dma_rx_trigger_dma()
849 desc->callback = pl011_dma_rx_callback; in pl011_dma_rx_trigger_dma()
850 desc->callback_param = uap; in pl011_dma_rx_trigger_dma()
851 dmarx->cookie = dmaengine_submit(desc); in pl011_dma_rx_trigger_dma()
854 uap->dmacr |= UART011_RXDMAE; in pl011_dma_rx_trigger_dma()
855 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_trigger_dma()
856 uap->dmarx.running = true; in pl011_dma_rx_trigger_dma()
858 uap->im &= ~UART011_RXIM; in pl011_dma_rx_trigger_dma()
859 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_trigger_dma()
867 * with the port spinlock uap->port.lock held.
873 struct tty_port *port = &uap->port.state->port; in pl011_dma_rx_chars()
875 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; in pl011_dma_rx_chars()
879 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_chars()
882 if (uap->dmarx.poll_rate) { in pl011_dma_rx_chars()
884 dmataken = dbuf->len - dmarx->last_residue; in pl011_dma_rx_chars()
887 pending -= dmataken; in pl011_dma_rx_chars()
898 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, in pl011_dma_rx_chars()
901 uap->port.icount.rx += dma_count; in pl011_dma_rx_chars()
903 dev_warn(uap->port.dev, in pl011_dma_rx_chars()
908 if (uap->dmarx.poll_rate) in pl011_dma_rx_chars()
909 dmarx->last_residue = dbuf->len; in pl011_dma_rx_chars()
934 dev_vdbg(uap->port.dev, in pl011_dma_rx_chars()
942 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_irq()
943 struct dma_chan *rxchan = dmarx->chan; in pl011_dma_rx_irq()
944 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ? in pl011_dma_rx_irq()
945 &dmarx->dbuf_b : &dmarx->dbuf_a; in pl011_dma_rx_irq()
956 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); in pl011_dma_rx_irq()
957 dmastat = rxchan->device->device_tx_status(rxchan, in pl011_dma_rx_irq()
958 dmarx->cookie, &state); in pl011_dma_rx_irq()
960 dev_err(uap->port.dev, "unable to pause DMA transfer\n"); in pl011_dma_rx_irq()
962 /* Disable RX DMA - incoming data will wait in the FIFO */ in pl011_dma_rx_irq()
963 uap->dmacr &= ~UART011_RXDMAE; in pl011_dma_rx_irq()
964 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_irq()
965 uap->dmarx.running = false; in pl011_dma_rx_irq()
967 pending = dbuf->len - state.residue; in pl011_dma_rx_irq()
969 /* Then we terminate the transfer - we now know our residue */ in pl011_dma_rx_irq()
976 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); in pl011_dma_rx_irq()
978 /* Switch buffer & re-trigger DMA job */ in pl011_dma_rx_irq()
979 dmarx->use_buf_b = !dmarx->use_buf_b; in pl011_dma_rx_irq()
981 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " in pl011_dma_rx_irq()
983 uap->im |= UART011_RXIM; in pl011_dma_rx_irq()
984 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_irq()
991 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_callback()
992 struct dma_chan *rxchan = dmarx->chan; in pl011_dma_rx_callback()
993 bool lastbuf = dmarx->use_buf_b; in pl011_dma_rx_callback()
994 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ? in pl011_dma_rx_callback()
995 &dmarx->dbuf_b : &dmarx->dbuf_a; in pl011_dma_rx_callback()
1007 uart_port_lock_irq(&uap->port); in pl011_dma_rx_callback()
1012 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); in pl011_dma_rx_callback()
1013 pending = dbuf->len - state.residue; in pl011_dma_rx_callback()
1015 /* Then we terminate the transfer - we now know our residue */ in pl011_dma_rx_callback()
1018 uap->dmarx.running = false; in pl011_dma_rx_callback()
1019 dmarx->use_buf_b = !lastbuf; in pl011_dma_rx_callback()
1023 uart_port_unlock_irq(&uap->port); in pl011_dma_rx_callback()
1029 dev_dbg(uap->port.dev, "could not retrigger RX DMA job " in pl011_dma_rx_callback()
1031 uap->im |= UART011_RXIM; in pl011_dma_rx_callback()
1032 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_callback()
1043 if (!uap->using_rx_dma) in pl011_dma_rx_stop()
1047 uap->dmacr &= ~UART011_RXDMAE; in pl011_dma_rx_stop()
1048 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_rx_stop()
1059 struct tty_port *port = &uap->port.state->port; in pl011_dma_rx_poll()
1060 struct pl011_dmarx_data *dmarx = &uap->dmarx; in pl011_dma_rx_poll()
1061 struct dma_chan *rxchan = uap->dmarx.chan; in pl011_dma_rx_poll()
1069 dbuf = dmarx->use_buf_b ? &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a; in pl011_dma_rx_poll()
1070 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); in pl011_dma_rx_poll()
1071 if (likely(state.residue < dmarx->last_residue)) { in pl011_dma_rx_poll()
1072 dmataken = dbuf->len - dmarx->last_residue; in pl011_dma_rx_poll()
1073 size = dmarx->last_residue - state.residue; in pl011_dma_rx_poll()
1074 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, in pl011_dma_rx_poll()
1077 dmarx->last_residue = state.residue; in pl011_dma_rx_poll()
1078 dmarx->last_jiffies = jiffies; in pl011_dma_rx_poll()
1086 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) in pl011_dma_rx_poll()
1087 > uap->dmarx.poll_timeout) { in pl011_dma_rx_poll()
1089 uart_port_lock_irqsave(&uap->port, &flags); in pl011_dma_rx_poll()
1091 uap->im |= UART011_RXIM; in pl011_dma_rx_poll()
1092 pl011_write(uap->im, uap, REG_IMSC); in pl011_dma_rx_poll()
1093 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_dma_rx_poll()
1095 uap->dmarx.running = false; in pl011_dma_rx_poll()
1097 del_timer(&uap->dmarx.timer); in pl011_dma_rx_poll()
1099 mod_timer(&uap->dmarx.timer, in pl011_dma_rx_poll()
1100 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_dma_rx_poll()
1108 if (!uap->dma_probed) in pl011_dma_startup()
1111 if (!uap->dmatx.chan) in pl011_dma_startup()
1114 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); in pl011_dma_startup()
1115 if (!uap->dmatx.buf) { in pl011_dma_startup()
1116 dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); in pl011_dma_startup()
1117 uap->port.fifosize = uap->fifosize; in pl011_dma_startup()
1121 uap->dmatx.len = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1124 uap->port.fifosize = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1125 uap->using_tx_dma = true; in pl011_dma_startup()
1127 if (!uap->dmarx.chan) in pl011_dma_startup()
1131 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_a, in pl011_dma_startup()
1134 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", in pl011_dma_startup()
1139 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_b, in pl011_dma_startup()
1142 dev_err(uap->port.dev, "failed to init DMA %s: %d\n", in pl011_dma_startup()
1144 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, in pl011_dma_startup()
1149 uap->using_rx_dma = true; in pl011_dma_startup()
1152 /* Turn on DMA error (RX/TX will be enabled on demand) */ in pl011_dma_startup()
1153 uap->dmacr |= UART011_DMAONERR; in pl011_dma_startup()
1154 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_startup()
1161 if (uap->vendor->dma_threshold) in pl011_dma_startup()
1165 if (uap->using_rx_dma) { in pl011_dma_startup()
1167 dev_dbg(uap->port.dev, "could not trigger initial " in pl011_dma_startup()
1169 if (uap->dmarx.poll_rate) { in pl011_dma_startup()
1170 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0); in pl011_dma_startup()
1171 mod_timer(&uap->dmarx.timer, in pl011_dma_startup()
1173 msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_dma_startup()
1174 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; in pl011_dma_startup()
1175 uap->dmarx.last_jiffies = jiffies; in pl011_dma_startup()
1182 if (!(uap->using_tx_dma || uap->using_rx_dma)) in pl011_dma_shutdown()
1185 /* Disable RX and TX DMA */ in pl011_dma_shutdown()
1186 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) in pl011_dma_shutdown()
1189 uart_port_lock_irq(&uap->port); in pl011_dma_shutdown()
1190 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); in pl011_dma_shutdown()
1191 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_shutdown()
1192 uart_port_unlock_irq(&uap->port); in pl011_dma_shutdown()
1194 if (uap->using_tx_dma) { in pl011_dma_shutdown()
1196 dmaengine_terminate_all(uap->dmatx.chan); in pl011_dma_shutdown()
1197 if (uap->dmatx.queued) { in pl011_dma_shutdown()
1198 dma_unmap_single(uap->dmatx.chan->device->dev, in pl011_dma_shutdown()
1199 uap->dmatx.dma, uap->dmatx.len, in pl011_dma_shutdown()
1201 uap->dmatx.queued = false; in pl011_dma_shutdown()
1204 kfree(uap->dmatx.buf); in pl011_dma_shutdown()
1205 uap->using_tx_dma = false; in pl011_dma_shutdown()
1208 if (uap->using_rx_dma) { in pl011_dma_shutdown()
1209 dmaengine_terminate_all(uap->dmarx.chan); in pl011_dma_shutdown()
1211 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, DMA_FROM_DEVICE); in pl011_dma_shutdown()
1212 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_b, DMA_FROM_DEVICE); in pl011_dma_shutdown()
1213 if (uap->dmarx.poll_rate) in pl011_dma_shutdown()
1214 del_timer_sync(&uap->dmarx.timer); in pl011_dma_shutdown()
1215 uap->using_rx_dma = false; in pl011_dma_shutdown()
1221 return uap->using_rx_dma; in pl011_dma_rx_available()
1226 return uap->using_rx_dma && uap->dmarx.running; in pl011_dma_rx_running()
1267 return -EIO; in pl011_dma_rx_trigger_dma()
1289 const int MAX_TX_DRAIN_ITERS = uap->port.fifosize * 2; in pl011_rs485_tx_stop()
1290 struct uart_port *port = &uap->port; in pl011_rs485_tx_stop()
1294 /* Wait until hardware tx queue is empty */ in pl011_rs485_tx_stop()
1297 dev_warn(port->dev, in pl011_rs485_tx_stop()
1298 "timeout while draining hardware tx queue\n"); in pl011_rs485_tx_stop()
1302 udelay(uap->rs485_tx_drain_interval); in pl011_rs485_tx_stop()
1306 if (port->rs485.delay_rts_after_send) in pl011_rs485_tx_stop()
1307 mdelay(port->rs485.delay_rts_after_send); in pl011_rs485_tx_stop()
1311 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in pl011_rs485_tx_stop()
1321 uap->rs485_tx_started = false; in pl011_rs485_tx_stop()
1329 uap->im &= ~UART011_TXIM; in pl011_stop_tx()
1330 pl011_write(uap->im, uap, REG_IMSC); in pl011_stop_tx()
1333 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) in pl011_stop_tx()
1339 /* Start TX with programmed I/O only (no DMA) */
1343 uap->im |= UART011_TXIM; in pl011_start_tx_pio()
1344 pl011_write(uap->im, uap, REG_IMSC); in pl011_start_tx_pio()
1350 struct uart_port *port = &uap->port; in pl011_rs485_tx_start()
1357 /* Disable receiver if half-duplex */ in pl011_rs485_tx_start()
1358 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) in pl011_rs485_tx_start()
1361 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) in pl011_rs485_tx_start()
1368 if (port->rs485.delay_rts_before_send) in pl011_rs485_tx_start()
1369 mdelay(port->rs485.delay_rts_before_send); in pl011_rs485_tx_start()
1371 uap->rs485_tx_started = true; in pl011_rs485_tx_start()
1379 if ((uap->port.rs485.flags & SER_RS485_ENABLED) && in pl011_start_tx()
1380 !uap->rs485_tx_started) in pl011_start_tx()
1392 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| in pl011_stop_rx()
1394 pl011_write(uap->im, uap, REG_IMSC); in pl011_stop_rx()
1413 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; in pl011_enable_ms()
1414 pl011_write(uap->im, uap, REG_IMSC); in pl011_enable_ms()
1418 __releases(&uap->port.lock) in pl011_rx_chars()
1419 __acquires(&uap->port.lock) in pl011_rx_chars()
1423 uart_port_unlock(&uap->port); in pl011_rx_chars()
1424 tty_flip_buffer_push(&uap->port.state->port); in pl011_rx_chars()
1431 dev_dbg(uap->port.dev, "could not trigger RX DMA job " in pl011_rx_chars()
1433 uap->im |= UART011_RXIM; in pl011_rx_chars()
1434 pl011_write(uap->im, uap, REG_IMSC); in pl011_rx_chars()
1438 if (uap->dmarx.poll_rate) { in pl011_rx_chars()
1439 uap->dmarx.last_jiffies = jiffies; in pl011_rx_chars()
1440 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; in pl011_rx_chars()
1441 mod_timer(&uap->dmarx.timer, in pl011_rx_chars()
1443 msecs_to_jiffies(uap->dmarx.poll_rate)); in pl011_rx_chars()
1448 uart_port_lock(&uap->port); in pl011_rx_chars()
1459 uap->port.icount.tx++; in pl011_tx_char()
1464 /* Returns true if tx interrupts have to be (kept) enabled */
1467 struct circ_buf *xmit = &uap->port.state->xmit; in pl011_tx_chars()
1468 int count = uap->fifosize >> 1; in pl011_tx_chars()
1470 if (uap->port.x_char) { in pl011_tx_chars()
1471 if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) in pl011_tx_chars()
1473 uap->port.x_char = 0; in pl011_tx_chars()
1474 --count; in pl011_tx_chars()
1476 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { in pl011_tx_chars()
1477 pl011_stop_tx(&uap->port); in pl011_tx_chars()
1486 if (likely(from_irq) && count-- == 0) in pl011_tx_chars()
1489 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) in pl011_tx_chars()
1492 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in pl011_tx_chars()
1496 uart_write_wakeup(&uap->port); in pl011_tx_chars()
1499 pl011_stop_tx(&uap->port); in pl011_tx_chars()
1511 delta = status ^ uap->old_status; in pl011_modem_status()
1512 uap->old_status = status; in pl011_modem_status()
1518 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); in pl011_modem_status()
1520 if (delta & uap->vendor->fr_dsr) in pl011_modem_status()
1521 uap->port.icount.dsr++; in pl011_modem_status()
1523 if (delta & uap->vendor->fr_cts) in pl011_modem_status()
1524 uart_handle_cts_change(&uap->port, in pl011_modem_status()
1525 status & uap->vendor->fr_cts); in pl011_modem_status()
1527 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); in pl011_modem_status()
1532 if (!uap->vendor->cts_event_workaround) in check_apply_cts_event_workaround()
1539 * WA: introduce 26ns(1 uart clk) delay before W1C; in check_apply_cts_event_workaround()
1554 uart_port_lock_irqsave(&uap->port, &flags); in pl011_int()
1555 status = pl011_read(uap, REG_RIS) & uap->im; in pl011_int()
1576 if (pass_counter-- == 0) in pl011_int()
1579 status = pl011_read(uap, REG_RIS) & uap->im; in pl011_int()
1584 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_int()
1594 /* Allow feature register bits to be inverted to work around errata */ in pl011_tx_empty()
1595 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; in pl011_tx_empty()
1597 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? in pl011_tx_empty()
1613 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR); in pl011_get_mctrl()
1614 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS); in pl011_get_mctrl()
1615 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG); in pl011_get_mctrl()
1640 if (port->status & UPSTAT_AUTORTS) { in pl011_set_mctrl()
1641 /* We need to disable auto-RTS if we want to turn RTS off */ in pl011_set_mctrl()
1656 uart_port_lock_irqsave(&uap->port, &flags); in pl011_break_ctl()
1658 if (break_state == -1) in pl011_break_ctl()
1663 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_break_ctl()
1684 * (including tx queue), so we're also fine with start_tx()'s caller in pl011_quiesce_irqs()
1731 pinctrl_pm_select_default_state(port->dev); in pl011_hwinit()
1736 retval = clk_prepare_enable(uap->clk); in pl011_hwinit()
1740 uap->port.uartclk = clk_get_rate(uap->clk); in pl011_hwinit()
1751 uap->im = pl011_read(uap, REG_IMSC); in pl011_hwinit()
1754 if (dev_get_platdata(uap->port.dev)) { in pl011_hwinit()
1757 plat = dev_get_platdata(uap->port.dev); in pl011_hwinit()
1758 if (plat->init) in pl011_hwinit()
1759 plat->init(); in pl011_hwinit()
1787 pl011_write(uap->im, uap, REG_IMSC); in pl011_allocate_irq()
1789 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap); in pl011_allocate_irq()
1802 uart_port_lock_irqsave(&uap->port, &flags); in pl011_enable_interrupts()
1813 for (i = 0; i < uap->fifosize * 2; ++i) { in pl011_enable_interrupts()
1820 uap->im = UART011_RTIM; in pl011_enable_interrupts()
1822 uap->im |= UART011_RXIM; in pl011_enable_interrupts()
1823 pl011_write(uap->im, uap, REG_IMSC); in pl011_enable_interrupts()
1824 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_enable_interrupts()
1832 uart_port_lock_irqsave(&uap->port, &flags); in pl011_unthrottle_rx()
1834 uap->im = UART011_RTIM; in pl011_unthrottle_rx()
1836 uap->im |= UART011_RXIM; in pl011_unthrottle_rx()
1838 pl011_write(uap->im, uap, REG_IMSC); in pl011_unthrottle_rx()
1841 if (uap->using_rx_dma) { in pl011_unthrottle_rx()
1842 uap->dmacr |= UART011_RXDMAE; in pl011_unthrottle_rx()
1843 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_unthrottle_rx()
1847 uart_port_unlock_irqrestore(&uap->port, flags); in pl011_unthrottle_rx()
1865 pl011_write(uap->vendor->ifls, uap, REG_IFLS); in pl011_startup()
1867 uart_port_lock_irq(&uap->port); in pl011_startup()
1873 if (!(port->rs485.flags & SER_RS485_ENABLED)) in pl011_startup()
1878 uart_port_unlock_irq(&uap->port); in pl011_startup()
1883 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; in pl011_startup()
1893 clk_disable_unprepare(uap->clk); in pl011_startup()
1912 uap->old_status = 0; in sbsa_uart_startup()
1938 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in pl011_disable_uart()
1939 uart_port_lock_irq(&uap->port); in pl011_disable_uart()
1944 uart_port_unlock_irq(&uap->port); in pl011_disable_uart()
1956 uart_port_lock_irq(&uap->port); in pl011_disable_interrupts()
1959 uap->im = 0; in pl011_disable_interrupts()
1960 pl011_write(uap->im, uap, REG_IMSC); in pl011_disable_interrupts()
1963 uart_port_unlock_irq(&uap->port); in pl011_disable_interrupts()
1975 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started) in pl011_shutdown()
1978 free_irq(uap->port.irq, uap); in pl011_shutdown()
1985 clk_disable_unprepare(uap->clk); in pl011_shutdown()
1987 pinctrl_pm_select_sleep_state(port->dev); in pl011_shutdown()
1989 if (dev_get_platdata(uap->port.dev)) { in pl011_shutdown()
1992 plat = dev_get_platdata(uap->port.dev); in pl011_shutdown()
1993 if (plat->exit) in pl011_shutdown()
1994 plat->exit(); in pl011_shutdown()
1997 if (uap->port.ops->flush_buffer) in pl011_shutdown()
1998 uap->port.ops->flush_buffer(port); in pl011_shutdown()
2008 free_irq(uap->port.irq, uap); in sbsa_uart_shutdown()
2010 if (uap->port.ops->flush_buffer) in sbsa_uart_shutdown()
2011 uap->port.ops->flush_buffer(port); in sbsa_uart_shutdown()
2017 port->read_status_mask = UART011_DR_OE | 255; in pl011_setup_status_masks()
2018 if (termios->c_iflag & INPCK) in pl011_setup_status_masks()
2019 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; in pl011_setup_status_masks()
2020 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in pl011_setup_status_masks()
2021 port->read_status_mask |= UART011_DR_BE; in pl011_setup_status_masks()
2026 port->ignore_status_mask = 0; in pl011_setup_status_masks()
2027 if (termios->c_iflag & IGNPAR) in pl011_setup_status_masks()
2028 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; in pl011_setup_status_masks()
2029 if (termios->c_iflag & IGNBRK) { in pl011_setup_status_masks()
2030 port->ignore_status_mask |= UART011_DR_BE; in pl011_setup_status_masks()
2035 if (termios->c_iflag & IGNPAR) in pl011_setup_status_masks()
2036 port->ignore_status_mask |= UART011_DR_OE; in pl011_setup_status_masks()
2042 if ((termios->c_cflag & CREAD) == 0) in pl011_setup_status_masks()
2043 port->ignore_status_mask |= UART_DUMMY_DR_RX; in pl011_setup_status_masks()
2057 if (uap->vendor->oversampling) in pl011_set_termios()
2066 port->uartclk / clkdiv); in pl011_set_termios()
2071 if (uap->dmarx.auto_poll_rate) in pl011_set_termios()
2072 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); in pl011_set_termios()
2075 if (baud > port->uartclk/16) in pl011_set_termios()
2076 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); in pl011_set_termios()
2078 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); in pl011_set_termios()
2080 switch (termios->c_cflag & CSIZE) { in pl011_set_termios()
2094 if (termios->c_cflag & CSTOPB) in pl011_set_termios()
2096 if (termios->c_cflag & PARENB) { in pl011_set_termios()
2098 if (!(termios->c_cflag & PARODD)) in pl011_set_termios()
2100 if (termios->c_cflag & CMSPAR) in pl011_set_termios()
2103 if (uap->fifosize > 1) in pl011_set_termios()
2106 bits = tty_get_frame_size(termios->c_cflag); in pl011_set_termios()
2111 * Update the per-port timeout. in pl011_set_termios()
2113 uart_update_timeout(port, termios->c_cflag, baud); in pl011_set_termios()
2118 * wait for the tx queue to empty. in pl011_set_termios()
2120 uap->rs485_tx_drain_interval = DIV_ROUND_UP(bits * 1000 * 1000, baud); in pl011_set_termios()
2124 if (UART_ENABLE_MS(port, termios->c_cflag)) in pl011_set_termios()
2127 if (port->rs485.flags & SER_RS485_ENABLED) in pl011_set_termios()
2128 termios->c_cflag &= ~CRTSCTS; in pl011_set_termios()
2132 if (termios->c_cflag & CRTSCTS) { in pl011_set_termios()
2137 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in pl011_set_termios()
2140 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in pl011_set_termios()
2143 if (uap->vendor->oversampling) { in pl011_set_termios()
2144 if (baud > port->uartclk / 16) in pl011_set_termios()
2156 if (uap->vendor->oversampling) { in pl011_set_termios()
2158 quot -= 1; in pl011_set_termios()
2160 quot -= 2; in pl011_set_termios()
2167 * ----------v----------v----------v----------v----- in pl011_set_termios()
2170 * ----------^----------^----------^----------^----- in pl011_set_termios()
2193 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); in sbsa_uart_set_termios()
2196 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); in sbsa_uart_set_termios()
2197 termios->c_cflag &= ~(CMSPAR | CRTSCTS); in sbsa_uart_set_termios()
2198 termios->c_cflag |= CS8 | CLOCAL; in sbsa_uart_set_termios()
2201 uart_update_timeout(port, CS8, uap->fixed_baud); in sbsa_uart_set_termios()
2210 return uap->port.type == PORT_AMBA ? uap->type : NULL; in pl011_type()
2219 port->type = PORT_AMBA; in pl011_config_port()
2228 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) in pl011_verify_port()
2229 ret = -EINVAL; in pl011_verify_port()
2230 if (ser->irq < 0 || ser->irq >= nr_irqs) in pl011_verify_port()
2231 ret = -EINVAL; in pl011_verify_port()
2232 if (ser->baud_base < 9600) in pl011_verify_port()
2233 ret = -EINVAL; in pl011_verify_port()
2234 if (port->mapbase != (unsigned long) ser->iomem_base) in pl011_verify_port()
2235 ret = -EINVAL; in pl011_verify_port()
2245 if (port->rs485.flags & SER_RS485_ENABLED) in pl011_rs485_config()
2249 if (rs485->flags & SER_RS485_ENABLED) { in pl011_rs485_config()
2254 port->status &= ~UPSTAT_AUTORTS; in pl011_rs485_config()
2331 struct uart_amba_port *uap = amba_ports[co->index]; in pl011_console_write()
2336 clk_enable(uap->clk); in pl011_console_write()
2339 if (uap->port.sysrq) in pl011_console_write()
2342 locked = uart_port_trylock(&uap->port); in pl011_console_write()
2344 uart_port_lock(&uap->port); in pl011_console_write()
2349 if (!uap->vendor->always_enabled) { in pl011_console_write()
2356 uart_console_write(&uap->port, s, count, pl011_console_putchar); in pl011_console_write()
2360 * TCR. Allow feature register bits to be inverted to work around in pl011_console_write()
2363 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) in pl011_console_write()
2364 & uap->vendor->fr_busy) in pl011_console_write()
2366 if (!uap->vendor->always_enabled) in pl011_console_write()
2370 uart_port_unlock(&uap->port); in pl011_console_write()
2373 clk_disable(uap->clk); in pl011_console_write()
2400 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); in pl011_console_get_options()
2402 if (uap->vendor->oversampling) { in pl011_console_get_options()
2424 if (co->index >= UART_NR) in pl011_console_setup()
2425 co->index = 0; in pl011_console_setup()
2426 uap = amba_ports[co->index]; in pl011_console_setup()
2428 return -ENODEV; in pl011_console_setup()
2431 pinctrl_pm_select_default_state(uap->port.dev); in pl011_console_setup()
2433 ret = clk_prepare(uap->clk); in pl011_console_setup()
2437 if (dev_get_platdata(uap->port.dev)) { in pl011_console_setup()
2440 plat = dev_get_platdata(uap->port.dev); in pl011_console_setup()
2441 if (plat->init) in pl011_console_setup()
2442 plat->init(); in pl011_console_setup()
2445 uap->port.uartclk = clk_get_rate(uap->clk); in pl011_console_setup()
2447 if (uap->vendor->fixed_options) { in pl011_console_setup()
2448 baud = uap->fixed_baud; in pl011_console_setup()
2457 return uart_set_options(&uap->port, co, baud, parity, bits, flow); in pl011_console_setup()
2461 * pl011_console_match - non-standard console matching
2476 * Returns 0 if console matches; otherwise non-zero to use default matching
2492 return -ENODEV; in pl011_console_match()
2495 return -ENODEV; in pl011_console_match()
2498 return -ENODEV; in pl011_console_match()
2507 port = &amba_ports[i]->port; in pl011_console_match()
2509 if (port->mapbase != addr) in pl011_console_match()
2512 co->index = i; in pl011_console_match()
2513 port->cons = co; in pl011_console_match()
2517 return -ENODEV; in pl011_console_match()
2528 .index = -1,
2536 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) in qdf2400_e44_putc()
2538 writel(c, port->membase + UART01x_DR); in qdf2400_e44_putc()
2539 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE)) in qdf2400_e44_putc()
2545 struct earlycon_device *dev = con->data; in qdf2400_e44_early_write()
2547 uart_console_write(&dev->port, s, n, qdf2400_e44_putc); in qdf2400_e44_early_write()
2552 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_putc()
2554 if (port->iotype == UPIO_MEM32) in pl011_putc()
2555 writel(c, port->membase + UART01x_DR); in pl011_putc()
2557 writeb(c, port->membase + UART01x_DR); in pl011_putc()
2558 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) in pl011_putc()
2564 struct earlycon_device *dev = con->data; in pl011_early_write()
2566 uart_console_write(&dev->port, s, n, pl011_putc); in pl011_early_write()
2572 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE) in pl011_getc()
2575 if (port->iotype == UPIO_MEM32) in pl011_getc()
2576 return readl(port->membase + UART01x_DR); in pl011_getc()
2578 return readb(port->membase + UART01x_DR); in pl011_getc()
2583 struct earlycon_device *dev = con->data; in pl011_early_read()
2587 ch = pl011_getc(&dev->port); in pl011_early_read()
2601 * On non-ACPI systems, earlycon is enabled by specifying
2615 if (!device->port.membase) in pl011_early_console_setup()
2616 return -ENODEV; in pl011_early_console_setup()
2618 device->con->write = pl011_early_write; in pl011_early_console_setup()
2619 device->con->read = pl011_early_read; in pl011_early_console_setup()
2624 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2633 * case, the SPCR code will detect the need for the E44 work-around,
2640 if (!device->port.membase) in qdf2400_e44_early_console_setup()
2641 return -ENODEV; in qdf2400_e44_early_console_setup()
2643 device->con->write = qdf2400_e44_early_write; in qdf2400_e44_early_console_setup()
2672 np = dev->of_node; in pl011_probe_dt_alias()
2689 …dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeratio… in pl011_probe_dt_alias()
2719 return -EBUSY; in pl011_find_free_port()
2724 struct uart_port *port = &uap->port; in pl011_get_rs485_mode()
2746 uap->port.dev = dev; in pl011_setup_port()
2747 uap->port.mapbase = mmiobase->start; in pl011_setup_port()
2748 uap->port.membase = base; in pl011_setup_port()
2749 uap->port.fifosize = uap->fifosize; in pl011_setup_port()
2750 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE); in pl011_setup_port()
2751 uap->port.flags = UPF_BOOT_AUTOCONF; in pl011_setup_port()
2752 uap->port.line = index; in pl011_setup_port()
2774 dev_err(uap->port.dev, in pl011_register_port()
2775 "Failed to register AMBA-PL011 driver\n"); in pl011_register_port()
2783 ret = uart_add_one_port(&amba_reg, &uap->port); in pl011_register_port()
2800 struct vendor_data *vendor = id->data; in pl011_probe()
2808 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), in pl011_probe()
2811 return -ENOMEM; in pl011_probe()
2813 uap->clk = devm_clk_get(&dev->dev, NULL); in pl011_probe()
2814 if (IS_ERR(uap->clk)) in pl011_probe()
2815 return PTR_ERR(uap->clk); in pl011_probe()
2817 uap->reg_offset = vendor->reg_offset; in pl011_probe()
2818 uap->vendor = vendor; in pl011_probe()
2819 uap->fifosize = vendor->get_fifosize(dev); in pl011_probe()
2820 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; in pl011_probe()
2821 uap->port.irq = dev->irq[0]; in pl011_probe()
2822 uap->port.ops = &amba_pl011_pops; in pl011_probe()
2823 uap->port.rs485_config = pl011_rs485_config; in pl011_probe()
2824 uap->port.rs485_supported = pl011_rs485_supported; in pl011_probe()
2825 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); in pl011_probe()
2827 if (device_property_read_u32(&dev->dev, "reg-io-width", &val) == 0) { in pl011_probe()
2830 uap->port.iotype = UPIO_MEM; in pl011_probe()
2833 uap->port.iotype = UPIO_MEM32; in pl011_probe()
2836 dev_warn(&dev->dev, "unsupported reg-io-width (%d)\n", in pl011_probe()
2838 return -EINVAL; in pl011_probe()
2842 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); in pl011_probe()
2855 uart_remove_one_port(&amba_reg, &uap->port); in pl011_remove()
2865 return -EINVAL; in pl011_suspend()
2867 return uart_suspend_port(&amba_reg, &uap->port); in pl011_suspend()
2875 return -EINVAL; in pl011_resume()
2877 return uart_resume_port(&amba_reg, &uap->port); in pl011_resume()
2894 if (pdev->dev.of_node) { in sbsa_uart_probe()
2895 struct device_node *np = pdev->dev.of_node; in sbsa_uart_probe()
2897 ret = of_property_read_u32(np, "current-speed", &baudrate); in sbsa_uart_probe()
2908 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), in sbsa_uart_probe()
2911 return -ENOMEM; in sbsa_uart_probe()
2916 uap->port.irq = ret; in sbsa_uart_probe()
2920 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n"); in sbsa_uart_probe()
2921 uap->vendor = &vendor_qdt_qdf2400_e44; in sbsa_uart_probe()
2924 uap->vendor = &vendor_sbsa; in sbsa_uart_probe()
2926 uap->reg_offset = uap->vendor->reg_offset; in sbsa_uart_probe()
2927 uap->fifosize = 32; in sbsa_uart_probe()
2928 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; in sbsa_uart_probe()
2929 uap->port.ops = &sbsa_uart_pops; in sbsa_uart_probe()
2930 uap->fixed_baud = baudrate; in sbsa_uart_probe()
2932 snprintf(uap->type, sizeof(uap->type), "SBSA"); in sbsa_uart_probe()
2936 ret = pl011_setup_port(&pdev->dev, uap, r, portnr); in sbsa_uart_probe()
2949 uart_remove_one_port(&amba_reg, &uap->port); in sbsa_uart_remove()
2955 { .compatible = "arm,sbsa-uart", },
2971 .name = "sbsa-uart",
2997 .name = "uart-pl011",