Lines Matching +full:dcd +full:- +full:override
1 // SPDX-License-Identifier: GPL-2.0+
99 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_modify_msr()
101 /* Override any modem control signals if needed */ in dw8250_modify_msr()
103 value |= d->msr_mask_on; in dw8250_modify_msr()
104 value &= ~d->msr_mask_off; in dw8250_modify_msr()
122 if (up->fcr & UART_FCR_ENABLE_FIFO) { in dw8250_force_idle()
123 lsr = p->serial_in(p, UART_LSR); in dw8250_force_idle()
128 (void)p->serial_in(p, UART_RX); in dw8250_force_idle()
133 void __iomem *offset = p->membase + (UART_LCR << p->regshift); in dw8250_check_lcr()
137 while (tries--) { in dw8250_check_lcr()
138 unsigned int lcr = p->serial_in(p, UART_LCR); in dw8250_check_lcr()
146 if (p->type == PORT_OCTEON) in dw8250_check_lcr()
150 if (p->iotype == UPIO_MEM32) in dw8250_check_lcr()
152 else if (p->iotype == UPIO_MEM32BE) in dw8250_check_lcr()
158 * FIXME: this deadlocks if port->lock is already held in dw8250_check_lcr()
159 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); in dw8250_check_lcr()
168 unsigned int delay_threshold = tries - 1000; in dw8250_tx_wait_empty()
171 while (tries--) { in dw8250_tx_wait_empty()
172 lsr = readb (p->membase + (UART_LSR << p->regshift)); in dw8250_tx_wait_empty()
173 up->lsr_saved_flags |= lsr & up->lsr_save_mask; in dw8250_tx_wait_empty()
180 * the buffer has still not emptied, allow more time for low- in dw8250_tx_wait_empty()
189 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_serial_out()
191 writeb(value, p->membase + (offset << p->regshift)); in dw8250_serial_out()
193 if (offset == UART_LCR && !d->uart_16550_compatible) in dw8250_serial_out()
208 unsigned int value = readb(p->membase + (offset << p->regshift)); in dw8250_serial_in()
218 value = (u8)__raw_readq(p->membase + (offset << p->regshift)); in dw8250_serial_inq()
225 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_serial_outq()
228 __raw_writeq(value, p->membase + (offset << p->regshift)); in dw8250_serial_outq()
230 __raw_readq(p->membase + (UART_LCR << p->regshift)); in dw8250_serial_outq()
232 if (offset == UART_LCR && !d->uart_16550_compatible) in dw8250_serial_outq()
239 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_serial_out32()
241 writel(value, p->membase + (offset << p->regshift)); in dw8250_serial_out32()
243 if (offset == UART_LCR && !d->uart_16550_compatible) in dw8250_serial_out32()
249 unsigned int value = readl(p->membase + (offset << p->regshift)); in dw8250_serial_in32()
256 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_serial_out32be()
258 iowrite32be(value, p->membase + (offset << p->regshift)); in dw8250_serial_out32be()
260 if (offset == UART_LCR && !d->uart_16550_compatible) in dw8250_serial_out32be()
266 unsigned int value = ioread32be(p->membase + (offset << p->regshift)); in dw8250_serial_in32be()
275 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_handle_irq()
276 unsigned int iir = p->serial_in(p, UART_IIR); in dw8250_handle_irq()
278 unsigned int quirks = d->pdata->quirks; in dw8250_handle_irq()
283 * There are ways to get Designware-based UARTs into a state where in dw8250_handle_irq()
290 * so we limit the workaround only to non-DMA mode. in dw8250_handle_irq()
292 if (!up->dma && rx_timeout) { in dw8250_handle_irq()
293 spin_lock_irqsave(&p->lock, flags); in dw8250_handle_irq()
297 (void) p->serial_in(p, UART_RX); in dw8250_handle_irq()
299 spin_unlock_irqrestore(&p->lock, flags); in dw8250_handle_irq()
303 if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) { in dw8250_handle_irq()
304 spin_lock_irqsave(&p->lock, flags); in dw8250_handle_irq()
306 spin_unlock_irqrestore(&p->lock, flags); in dw8250_handle_irq()
319 (void)p->serial_in(p, d->pdata->usr_reg); in dw8250_handle_irq()
333 rate = clk_get_rate(d->clk); in dw8250_clk_work_cb()
337 up = serial8250_get_port(d->data.line); in dw8250_clk_work_cb()
339 serial8250_update_uartclk(&up->port, rate); in dw8250_clk_work_cb()
352 * the clk and tty-port mutexes lock. It happens if clock rate change in dw8250_clk_notifier_cb()
354 * tty-port mutex lock and clk_set_rate() function invocation and in dw8250_clk_notifier_cb()
355 * vise-versa. Anyway if we didn't have the reference clock alteration in dw8250_clk_notifier_cb()
360 queue_work(system_unbound_wq, &d->clk_work); in dw8250_clk_notifier_cb()
371 pm_runtime_get_sync(port->dev); in dw8250_do_pm()
376 pm_runtime_put_sync_suspend(port->dev); in dw8250_do_pm()
383 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_set_termios()
387 clk_disable_unprepare(d->clk); in dw8250_set_termios()
388 rate = clk_round_rate(d->clk, newrate); in dw8250_set_termios()
391 * Note that any clock-notifer worker will block in in dw8250_set_termios()
394 ret = clk_set_rate(d->clk, newrate); in dw8250_set_termios()
396 p->uartclk = rate; in dw8250_set_termios()
398 clk_prepare_enable(d->clk); in dw8250_set_termios()
406 unsigned int mcr = p->serial_in(p, UART_MCR); in dw8250_set_ldisc()
408 if (up->capabilities & UART_CAP_IRDA) { in dw8250_set_ldisc()
409 if (termios->c_line == N_IRDA) in dw8250_set_ldisc()
414 p->serial_out(p, UART_MCR, mcr); in dw8250_set_ldisc()
434 return param == chan->device->dev; in dw8250_idma_filter()
449 struct uart_port *up = &p->port; in dw8250_prepare_tx_dma()
450 struct uart_8250_dma *dma = p->dma; in dw8250_prepare_tx_dma()
454 val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) | in dw8250_prepare_tx_dma()
455 RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) | in dw8250_prepare_tx_dma()
462 struct uart_port *up = &p->port; in dw8250_prepare_rx_dma()
463 struct uart_8250_dma *dma = p->dma; in dw8250_prepare_rx_dma()
467 val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) | in dw8250_prepare_rx_dma()
468 RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) | in dw8250_prepare_rx_dma()
475 unsigned int quirks = data->pdata ? data->pdata->quirks : 0; in dw8250_quirks()
476 u32 cpr_value = data->pdata ? data->pdata->cpr_value : 0; in dw8250_quirks()
479 data->data.cpr_value = cpr_value; in dw8250_quirks()
483 p->serial_in = dw8250_serial_inq; in dw8250_quirks()
484 p->serial_out = dw8250_serial_outq; in dw8250_quirks()
485 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; in dw8250_quirks()
486 p->type = PORT_OCTEON; in dw8250_quirks()
487 data->skip_autocfg = true; in dw8250_quirks()
492 p->serial_out = dw8250_serial_out38x; in dw8250_quirks()
494 p->set_termios = dw8250_do_set_termios; in dw8250_quirks()
496 data->data.dma.txconf.device_fc = 1; in dw8250_quirks()
497 data->data.dma.rxconf.device_fc = 1; in dw8250_quirks()
498 data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma; in dw8250_quirks()
499 data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma; in dw8250_quirks()
502 p->iotype = UPIO_MEM32; in dw8250_quirks()
503 p->regshift = 2; in dw8250_quirks()
504 p->serial_in = dw8250_serial_in32; in dw8250_quirks()
505 data->uart_16550_compatible = true; in dw8250_quirks()
508 /* Platforms with iDMA 64-bit */ in dw8250_quirks()
509 if (platform_get_resource_byname(to_platform_device(p->dev), in dw8250_quirks()
511 data->data.dma.rx_param = p->dev->parent; in dw8250_quirks()
512 data->data.dma.tx_param = p->dev->parent; in dw8250_quirks()
513 data->data.dma.fn = dw8250_idma_filter; in dw8250_quirks()
530 struct uart_port *p = &up->port; in dw8250_probe()
531 struct device *dev = &pdev->dev; in dw8250_probe()
538 return dev_err_probe(dev, -EINVAL, "no registers defined\n"); in dw8250_probe()
540 spin_lock_init(&p->lock); in dw8250_probe()
541 p->handle_irq = dw8250_handle_irq; in dw8250_probe()
542 p->pm = dw8250_do_pm; in dw8250_probe()
543 p->type = PORT_8250; in dw8250_probe()
544 p->flags = UPF_FIXED_PORT; in dw8250_probe()
545 p->dev = dev; in dw8250_probe()
546 p->set_ldisc = dw8250_set_ldisc; in dw8250_probe()
547 p->set_termios = dw8250_set_termios; in dw8250_probe()
551 return -ENOMEM; in dw8250_probe()
553 data->data.dma.fn = dw8250_fallback_dma_filter; in dw8250_probe()
554 data->pdata = device_get_match_data(p->dev); in dw8250_probe()
555 p->private_data = &data->data; in dw8250_probe()
557 data->uart_16550_compatible = device_property_read_bool(dev, in dw8250_probe()
558 "snps,uart-16550-compatible"); in dw8250_probe()
560 p->mapbase = regs->start; in dw8250_probe()
561 p->mapsize = resource_size(regs); in dw8250_probe()
563 p->membase = devm_ioremap(dev, p->mapbase, p->mapsize); in dw8250_probe()
564 if (!p->membase) in dw8250_probe()
565 return -ENOMEM; in dw8250_probe()
568 /* no interrupt -> fall back to polling */ in dw8250_probe()
569 if (err == -ENXIO) in dw8250_probe()
574 switch (p->iotype) { in dw8250_probe()
576 p->serial_in = dw8250_serial_in; in dw8250_probe()
577 p->serial_out = dw8250_serial_out; in dw8250_probe()
580 p->serial_in = dw8250_serial_in32; in dw8250_probe()
581 p->serial_out = dw8250_serial_out32; in dw8250_probe()
584 p->serial_in = dw8250_serial_in32be; in dw8250_probe()
585 p->serial_out = dw8250_serial_out32be; in dw8250_probe()
588 return -ENODEV; in dw8250_probe()
591 if (device_property_read_bool(dev, "dcd-override")) { in dw8250_probe()
592 /* Always report DCD as active */ in dw8250_probe()
593 data->msr_mask_on |= UART_MSR_DCD; in dw8250_probe()
594 data->msr_mask_off |= UART_MSR_DDCD; in dw8250_probe()
597 if (device_property_read_bool(dev, "dsr-override")) { in dw8250_probe()
599 data->msr_mask_on |= UART_MSR_DSR; in dw8250_probe()
600 data->msr_mask_off |= UART_MSR_DDSR; in dw8250_probe()
603 if (device_property_read_bool(dev, "cts-override")) { in dw8250_probe()
605 data->msr_mask_on |= UART_MSR_CTS; in dw8250_probe()
606 data->msr_mask_off |= UART_MSR_DCTS; in dw8250_probe()
609 if (device_property_read_bool(dev, "ri-override")) { in dw8250_probe()
611 data->msr_mask_off |= UART_MSR_RI; in dw8250_probe()
612 data->msr_mask_off |= UART_MSR_TERI; in dw8250_probe()
616 data->clk = devm_clk_get_optional(dev, "baudclk"); in dw8250_probe()
617 if (data->clk == NULL) in dw8250_probe()
618 data->clk = devm_clk_get_optional(dev, NULL); in dw8250_probe()
619 if (IS_ERR(data->clk)) in dw8250_probe()
620 return PTR_ERR(data->clk); in dw8250_probe()
622 INIT_WORK(&data->clk_work, dw8250_clk_work_cb); in dw8250_probe()
623 data->clk_notifier.notifier_call = dw8250_clk_notifier_cb; in dw8250_probe()
625 err = clk_prepare_enable(data->clk); in dw8250_probe()
629 err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->clk); in dw8250_probe()
633 if (data->clk) in dw8250_probe()
634 p->uartclk = clk_get_rate(data->clk); in dw8250_probe()
637 if (!p->uartclk) in dw8250_probe()
638 return dev_err_probe(dev, -EINVAL, "clock rate not defined\n"); in dw8250_probe()
640 data->pclk = devm_clk_get_optional(dev, "apb_pclk"); in dw8250_probe()
641 if (IS_ERR(data->pclk)) in dw8250_probe()
642 return PTR_ERR(data->pclk); in dw8250_probe()
644 err = clk_prepare_enable(data->pclk); in dw8250_probe()
648 err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->pclk); in dw8250_probe()
652 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL); in dw8250_probe()
653 if (IS_ERR(data->rst)) in dw8250_probe()
654 return PTR_ERR(data->rst); in dw8250_probe()
656 reset_control_deassert(data->rst); in dw8250_probe()
658 err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst); in dw8250_probe()
665 if (data->uart_16550_compatible) in dw8250_probe()
666 p->handle_irq = NULL; in dw8250_probe()
668 if (!data->skip_autocfg) in dw8250_probe()
672 if (p->fifosize) { in dw8250_probe()
673 data->data.dma.rxconf.src_maxburst = p->fifosize / 4; in dw8250_probe()
674 data->data.dma.txconf.dst_maxburst = p->fifosize / 4; in dw8250_probe()
675 up->dma = &data->data.dma; in dw8250_probe()
678 data->data.line = serial8250_register_8250_port(up); in dw8250_probe()
679 if (data->data.line < 0) in dw8250_probe()
680 return data->data.line; in dw8250_probe()
687 if (data->clk) { in dw8250_probe()
688 err = clk_notifier_register(data->clk, &data->clk_notifier); in dw8250_probe()
691 queue_work(system_unbound_wq, &data->clk_work); in dw8250_probe()
705 struct device *dev = &pdev->dev; in dw8250_remove()
709 if (data->clk) { in dw8250_remove()
710 clk_notifier_unregister(data->clk, &data->clk_notifier); in dw8250_remove()
712 flush_work(&data->clk_work); in dw8250_remove()
715 serial8250_unregister_port(data->data.line); in dw8250_remove()
727 serial8250_suspend_port(data->data.line); in dw8250_suspend()
736 serial8250_resume_port(data->data.line); in dw8250_resume()
745 clk_disable_unprepare(data->clk); in dw8250_runtime_suspend()
747 clk_disable_unprepare(data->pclk); in dw8250_runtime_suspend()
756 clk_prepare_enable(data->pclk); in dw8250_runtime_resume()
758 clk_prepare_enable(data->clk); in dw8250_runtime_resume()
794 { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
795 { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
796 { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
797 { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
798 { .compatible = "sophgo,sg2044-uart", .data = &dw8250_skip_set_rate_data },
799 { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data },
829 .name = "dw-apb-uart",
843 MODULE_ALIAS("platform:dw-apb-uart");