437 	u32 val;  in tb_dp_cm_handshake()
473 static inline u32 tb_dp_cap_get_rate(u32 val)  in tb_dp_cap_get_rate()
475 	u32 rate = (val & DP_COMMON_CAP_RATE_MASK) >> DP_COMMON_CAP_RATE_SHIFT;  in tb_dp_cap_get_rate()
496 static inline u32 tb_dp_cap_get_rate_ext(u32 val)  in tb_dp_cap_get_rate_ext()
513 static inline u32 tb_dp_cap_set_rate(u32 val, u32 rate)  in tb_dp_cap_set_rate()
536 static inline u32 tb_dp_cap_get_lanes(u32 val)  in tb_dp_cap_get_lanes()
538 	u32 lanes = (val & DP_COMMON_CAP_LANES_MASK) >> DP_COMMON_CAP_LANES_SHIFT;  in tb_dp_cap_get_lanes()
552 static inline u32 tb_dp_cap_set_lanes(u32 val, u32 lanes)  in tb_dp_cap_set_lanes()
581 static int tb_dp_reduce_bandwidth(int max_bw, u32 in_rate, u32 in_lanes,  in tb_dp_reduce_bandwidth()
582 				  u32 out_rate, u32 out_lanes, u32 *new_rate,  in tb_dp_reduce_bandwidth()
583 				  u32 *new_lanes)  in tb_dp_reduce_bandwidth()
585 	static const u32 dp_bw[][2] = {  in tb_dp_reduce_bandwidth()
626 	u32 out_dp_cap, out_rate, out_lanes, in_dp_cap, in_rate, in_lanes, bw;  in tb_dp_xchg_caps()
686 		u32 new_rate, new_lanes, new_bw;  in tb_dp_xchg_caps()
728 	u32 out_dp_cap, out_rate, out_lanes;  in tb_dp_bandwidth_alloc_mode_enable()
729 	u32 in_dp_cap, in_rate, in_lanes;  in tb_dp_bandwidth_alloc_mode_enable()
730 	u32 rate, lanes;  in tb_dp_bandwidth_alloc_mode_enable()
906 	u32 cap;  in tb_dp_bandwidth_mode_maximum_bandwidth()
1060 static int tb_dp_read_dprx(struct tb_tunnel *tunnel, u32 *rate, u32 *lanes,  in tb_dp_read_dprx()
1071 		u32 val;  in tb_dp_read_dprx()
1093 static int tb_dp_read_cap(struct tb_tunnel *tunnel, unsigned int cap, u32 *rate,  in tb_dp_read_cap()
1094 			  u32 *lanes)  in tb_dp_read_cap()
1097 	u32 val;  in tb_dp_read_cap()
1152 	u32 rate = 0, lanes = 0;  in tb_dp_consumed_bandwidth()
1285 	u32 dp_cap, rate, lanes;  in tb_dp_dump()