Lines Matching refs:cmd
215 u32 cmd; in pci2cio_wait_completion() local
219 icm->vnd_cap + PCIE2CIO_CMD, &cmd); in pci2cio_wait_completion()
220 if (!(cmd & PCIE2CIO_CMD_START)) { in pci2cio_wait_completion()
221 if (cmd & PCIE2CIO_CMD_TIMEOUT) in pci2cio_wait_completion()
237 u32 cmd; in pcie2cio_read() local
239 cmd = index; in pcie2cio_read()
240 cmd |= (port << PCIE2CIO_CMD_PORT_SHIFT) & PCIE2CIO_CMD_PORT_MASK; in pcie2cio_read()
241 cmd |= (cs << PCIE2CIO_CMD_CS_SHIFT) & PCIE2CIO_CMD_CS_MASK; in pcie2cio_read()
242 cmd |= PCIE2CIO_CMD_START; in pcie2cio_read()
243 pci_write_config_dword(pdev, vnd_cap + PCIE2CIO_CMD, cmd); in pcie2cio_read()
258 u32 cmd; in pcie2cio_write() local
262 cmd = index; in pcie2cio_write()
263 cmd |= (port << PCIE2CIO_CMD_PORT_SHIFT) & PCIE2CIO_CMD_PORT_MASK; in pcie2cio_write()
264 cmd |= (cs << PCIE2CIO_CMD_CS_SHIFT) & PCIE2CIO_CMD_CS_MASK; in pcie2cio_write()
265 cmd |= PCIE2CIO_CMD_WRITE | PCIE2CIO_CMD_START; in pcie2cio_write()
266 pci_write_config_dword(pdev, vnd_cap + PCIE2CIO_CMD, cmd); in pcie2cio_write()
595 u8 cmd; in icm_fr_disconnect_xdomain_paths() local
599 cmd = NHI_MAILBOX_DISCONNECT_PA; in icm_fr_disconnect_xdomain_paths()
601 cmd = NHI_MAILBOX_DISCONNECT_PB; in icm_fr_disconnect_xdomain_paths()
603 nhi_mailbox_cmd(tb->nhi, cmd, 1); in icm_fr_disconnect_xdomain_paths()
605 nhi_mailbox_cmd(tb->nhi, cmd, 2); in icm_fr_disconnect_xdomain_paths()