20 static void cvm_oct_spxx_int_pr(union cvmx_spxx_int_reg spx_int_reg, int index)  in cvm_oct_spxx_int_pr()  argument
23 		pr_err("SPI%d: SRX Spi4 interface down\n", index);  in cvm_oct_spxx_int_pr()
25 		pr_err("SPI%d: SRX Spi4 Calendar table parity error\n", index);  in cvm_oct_spxx_int_pr()
28 		       index);  in cvm_oct_spxx_int_pr()
30 		pr_err("SPI%d: SRX Spi4 DIP4 error\n", index);  in cvm_oct_spxx_int_pr()
33 		       index);  in cvm_oct_spxx_int_pr()
36 		       index);  in cvm_oct_spxx_int_pr()
39 		       index);  in cvm_oct_spxx_int_pr()
42 		       index);  in cvm_oct_spxx_int_pr()
44 		pr_err("SPI%d: SRX Spi4 async FIFO overflow\n", index);  in cvm_oct_spxx_int_pr()
47 		       index);  in cvm_oct_spxx_int_pr()
49 		pr_err("SPI%d: SRX Port out of range\n", index);  in cvm_oct_spxx_int_pr()
52 static void cvm_oct_stxx_int_pr(union cvmx_stxx_int_reg stx_int_reg, int index)  in cvm_oct_stxx_int_pr()  argument
56 		       index);  in cvm_oct_stxx_int_pr()
59 		       index);  in cvm_oct_stxx_int_pr()
61 		pr_err("SPI%d: STX Unexpected framing sequence\n", index);  in cvm_oct_stxx_int_pr()
64 		       index);  in cvm_oct_stxx_int_pr()
67 		       index);  in cvm_oct_stxx_int_pr()
69 		pr_err("SPI%d: STX Spi4 FIFO overflow error\n", index);  in cvm_oct_stxx_int_pr()
71 		pr_err("SPI%d: STX Transmit packet burst too big\n", index);  in cvm_oct_stxx_int_pr()
74 		       index, 1);  in cvm_oct_stxx_int_pr()
77 		       index, 0);  in cvm_oct_stxx_int_pr()
80 static irqreturn_t cvm_oct_spi_spx_int(int index)  in cvm_oct_spi_spx_int()  argument
85 	spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(index));  in cvm_oct_spi_spx_int()
86 	cvmx_write_csr(CVMX_SPXX_INT_REG(index), spx_int_reg.u64);  in cvm_oct_spi_spx_int()
87 	if (!need_retrain[index]) {  in cvm_oct_spi_spx_int()
88 		spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(index));  in cvm_oct_spi_spx_int()
89 		cvm_oct_spxx_int_pr(spx_int_reg, index);  in cvm_oct_spi_spx_int()
92 	stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(index));  in cvm_oct_spi_spx_int()
93 	cvmx_write_csr(CVMX_STXX_INT_REG(index), stx_int_reg.u64);  in cvm_oct_spi_spx_int()
94 	if (!need_retrain[index]) {  in cvm_oct_spi_spx_int()
95 		stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(index));  in cvm_oct_spi_spx_int()
96 		cvm_oct_stxx_int_pr(stx_int_reg, index);  in cvm_oct_spi_spx_int()
99 	cvmx_write_csr(CVMX_SPXX_INT_MSK(index), 0);  in cvm_oct_spi_spx_int()
100 	cvmx_write_csr(CVMX_STXX_INT_MSK(index), 0);  in cvm_oct_spi_spx_int()
101 	need_retrain[index] = 1;  in cvm_oct_spi_spx_int()