Lines Matching defs:fc_regs
416 struct fc_regs { struct
417 u32 USB_CONTROL; /* (0x0000) USB Control */
418 u32 USB_STATUS; /* (0x0004) USB Status */
419 u32 USB_ADDRESS; /* (0x0008) USB Address */
420 u32 UTMI_CHARACTER_1; /* (0x000C) UTMI Setting */
421 u32 TEST_CONTROL; /* (0x0010) TEST Control */
422 u32 reserved_14; /* (0x0014) Reserved */
423 u32 SETUP_DATA0; /* (0x0018) Setup Data0 */
424 u32 SETUP_DATA1; /* (0x001C) Setup Data1 */
425 u32 USB_INT_STA; /* (0x0020) USB Interrupt Status */
426 u32 USB_INT_ENA; /* (0x0024) USB Interrupt Enable */
427 u32 EP0_CONTROL; /* (0x0028) EP0 Control */
428 u32 EP0_STATUS; /* (0x002C) EP0 Status */
429 u32 EP0_INT_ENA; /* (0x0030) EP0 Interrupt Enable */
430 u32 EP0_LENGTH; /* (0x0034) EP0 Length */
431 u32 EP0_READ; /* (0x0038) EP0 Read */
432 u32 EP0_WRITE; /* (0x003C) EP0 Write */
434 struct ep_regs EP_REGS[REG_EP_NUM]; /* Endpoint Register */
436 u8 reserved_220[0x1000 - 0x220]; /* (0x0220:0x0FFF) Reserved */
438 u32 AHBSCTR; /* (0x1000) AHBSCTR */
439 u32 AHBMCTR; /* (0x1004) AHBMCTR */
440 u32 AHBBINT; /* (0x1008) AHBBINT */
441 u32 AHBBINTEN; /* (0x100C) AHBBINTEN */
442 u32 EPCTR; /* (0x1010) EPCTR */
443 u32 USBF_EPTEST; /* (0x1014) USBF_EPTEST */
445 u8 reserved_1018[0x20 - 0x18]; /* (0x1018:0x101F) Reserved */
447 u32 USBSSVER; /* (0x1020) USBSSVER */
448 u32 USBSSCONF; /* (0x1024) USBSSCONF */
450 u8 reserved_1028[0x110 - 0x28]; /* (0x1028:0x110F) Reserved */
452 struct ep_dcr EP_DCR[REG_EP_NUM]; /* */
454 u8 reserved_1200[0x1000 - 0x200]; /* Reserved */