95 	u32 pmuctl, tmp, pllctl;  in ssb_pmu0_pllinit_r0()  local
107 	pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);  in ssb_pmu0_pllinit_r0()
108 	if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {  in ssb_pmu0_pllinit_r0()
168 	pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);  in ssb_pmu0_pllinit_r0()
169 	pmuctl &= ~SSB_CHIPCO_PMU_CTL_ILP_DIV;  in ssb_pmu0_pllinit_r0()
170 	pmuctl |= (((crystalfreq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT)  in ssb_pmu0_pllinit_r0()
172 	pmuctl &= ~SSB_CHIPCO_PMU_CTL_XTALFREQ;  in ssb_pmu0_pllinit_r0()
173 	pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;  in ssb_pmu0_pllinit_r0()
174 	chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);  in ssb_pmu0_pllinit_r0()
227 	u32 tmp, pllctl, pmuctl;  in ssb_pmu1_pllinit_r0()  local
246 	pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);  in ssb_pmu1_pllinit_r0()
247 	if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {  in ssb_pmu1_pllinit_r0()
309 	pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);  in ssb_pmu1_pllinit_r0()
310 	pmuctl &= ~(SSB_CHIPCO_PMU_CTL_ILP_DIV | SSB_CHIPCO_PMU_CTL_XTALFREQ);  in ssb_pmu1_pllinit_r0()
311 	pmuctl |= ((((u32)e->freq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT)  in ssb_pmu1_pllinit_r0()
313 	pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;  in ssb_pmu1_pllinit_r0()
314 	chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);  in ssb_pmu1_pllinit_r0()