Lines Matching refs:cc
22 static u32 ssb_chipco_pll_read(struct ssb_chipcommon *cc, u32 offset) in ssb_chipco_pll_read() argument
24 chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset); in ssb_chipco_pll_read()
25 return chipco_read32(cc, SSB_CHIPCO_PLLCTL_DATA); in ssb_chipco_pll_read()
28 static void ssb_chipco_pll_write(struct ssb_chipcommon *cc, in ssb_chipco_pll_write() argument
31 chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset); in ssb_chipco_pll_write()
32 chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value); in ssb_chipco_pll_write()
35 static void ssb_chipco_regctl_maskset(struct ssb_chipcommon *cc, in ssb_chipco_regctl_maskset() argument
40 chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR); in ssb_chipco_regctl_maskset()
41 chipco_write32(cc, SSB_CHIPCO_REGCTL_ADDR, offset); in ssb_chipco_regctl_maskset()
42 chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR); in ssb_chipco_regctl_maskset()
43 value = chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA); in ssb_chipco_regctl_maskset()
46 chipco_write32(cc, SSB_CHIPCO_REGCTL_DATA, value); in ssb_chipco_regctl_maskset()
47 chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA); in ssb_chipco_regctl_maskset()
90 static void ssb_pmu0_pllinit_r0(struct ssb_chipcommon *cc, in ssb_pmu0_pllinit_r0() argument
93 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu0_pllinit_r0()
104 cc->pmu.crystalfreq = e->freq; in ssb_pmu0_pllinit_r0()
107 pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL); in ssb_pmu0_pllinit_r0()
113 dev_info(cc->dev->dev, "Programming PLL to %u.%03u MHz\n", in ssb_pmu0_pllinit_r0()
119 chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, in ssb_pmu0_pllinit_r0()
121 chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, in ssb_pmu0_pllinit_r0()
125 chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, in ssb_pmu0_pllinit_r0()
127 chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, in ssb_pmu0_pllinit_r0()
134 tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); in ssb_pmu0_pllinit_r0()
139 tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); in ssb_pmu0_pllinit_r0()
141 dev_emerg(cc->dev->dev, "Failed to turn the PLL off!\n"); in ssb_pmu0_pllinit_r0()
144 pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0); in ssb_pmu0_pllinit_r0()
149 ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL0, pllctl); in ssb_pmu0_pllinit_r0()
152 pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL1); in ssb_pmu0_pllinit_r0()
159 ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL1, pllctl); in ssb_pmu0_pllinit_r0()
162 pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL2); in ssb_pmu0_pllinit_r0()
165 ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL2, pllctl); in ssb_pmu0_pllinit_r0()
168 pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL); in ssb_pmu0_pllinit_r0()
174 chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl); in ssb_pmu0_pllinit_r0()
221 static void ssb_pmu1_pllinit_r0(struct ssb_chipcommon *cc, in ssb_pmu1_pllinit_r0() argument
224 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu1_pllinit_r0()
233 cc->pmu.crystalfreq = 20000; in ssb_pmu1_pllinit_r0()
243 cc->pmu.crystalfreq = e->freq; in ssb_pmu1_pllinit_r0()
246 pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL); in ssb_pmu1_pllinit_r0()
252 dev_info(cc->dev->dev, "Programming PLL to %u.%03u MHz\n", in ssb_pmu1_pllinit_r0()
258 chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, in ssb_pmu1_pllinit_r0()
261 chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, in ssb_pmu1_pllinit_r0()
271 tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); in ssb_pmu1_pllinit_r0()
276 tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST); in ssb_pmu1_pllinit_r0()
278 dev_emerg(cc->dev->dev, "Failed to turn the PLL off!\n"); in ssb_pmu1_pllinit_r0()
281 pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0); in ssb_pmu1_pllinit_r0()
285 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, pllctl); in ssb_pmu1_pllinit_r0()
288 pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL2); in ssb_pmu1_pllinit_r0()
292 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, pllctl); in ssb_pmu1_pllinit_r0()
295 pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL3); in ssb_pmu1_pllinit_r0()
298 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, pllctl); in ssb_pmu1_pllinit_r0()
302 pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL5); in ssb_pmu1_pllinit_r0()
305 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, pllctl); in ssb_pmu1_pllinit_r0()
309 pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL); in ssb_pmu1_pllinit_r0()
314 chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl); in ssb_pmu1_pllinit_r0()
317 static void ssb_pmu_pll_init(struct ssb_chipcommon *cc) in ssb_pmu_pll_init() argument
319 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu_pll_init()
333 ssb_pmu1_pllinit_r0(cc, crystalfreq); in ssb_pmu_pll_init()
336 ssb_pmu0_pllinit_r0(cc, crystalfreq); in ssb_pmu_pll_init()
341 ssb_pmu0_pllinit_r0(cc, crystalfreq); in ssb_pmu_pll_init()
344 if (cc->pmu.rev == 2) { in ssb_pmu_pll_init()
345 chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A); in ssb_pmu_pll_init()
346 chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0); in ssb_pmu_pll_init()
352 dev_err(cc->dev->dev, "ERROR: PLL init unknown for device %04X\n", in ssb_pmu_pll_init()
423 static void ssb_pmu_resources_init(struct ssb_chipcommon *cc) in ssb_pmu_resources_init() argument
425 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu_resources_init()
448 if (chipco_read32(cc, SSB_CHIPCO_CHIPSTAT) & in ssb_pmu_resources_init()
474 dev_err(cc->dev->dev, "ERROR: PMU resource config unknown for device %04X\n", in ssb_pmu_resources_init()
480 chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL, in ssb_pmu_resources_init()
482 chipco_write32(cc, SSB_CHIPCO_PMU_RES_UPDNTM, in ssb_pmu_resources_init()
488 chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL, in ssb_pmu_resources_init()
492 chipco_write32(cc, SSB_CHIPCO_PMU_RES_DEPMSK, in ssb_pmu_resources_init()
496 chipco_set32(cc, SSB_CHIPCO_PMU_RES_DEPMSK, in ssb_pmu_resources_init()
500 chipco_mask32(cc, SSB_CHIPCO_PMU_RES_DEPMSK, in ssb_pmu_resources_init()
511 chipco_write32(cc, SSB_CHIPCO_PMU_MINRES_MSK, min_msk); in ssb_pmu_resources_init()
513 chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk); in ssb_pmu_resources_init()
517 void ssb_pmu_init(struct ssb_chipcommon *cc) in ssb_pmu_init() argument
521 if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU)) in ssb_pmu_init()
524 pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP); in ssb_pmu_init()
525 cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION); in ssb_pmu_init()
527 dev_dbg(cc->dev->dev, "Found rev %u PMU (capabilities 0x%08X)\n", in ssb_pmu_init()
528 cc->pmu.rev, pmucap); in ssb_pmu_init()
530 if (cc->pmu.rev == 1) in ssb_pmu_init()
531 chipco_mask32(cc, SSB_CHIPCO_PMU_CTL, in ssb_pmu_init()
534 chipco_set32(cc, SSB_CHIPCO_PMU_CTL, in ssb_pmu_init()
536 ssb_pmu_pll_init(cc); in ssb_pmu_init()
537 ssb_pmu_resources_init(cc); in ssb_pmu_init()
540 void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc, in ssb_pmu_set_ldo_voltage() argument
543 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu_set_ldo_voltage()
586 ssb_chipco_regctl_maskset(cc, addr, ~(mask << shift), in ssb_pmu_set_ldo_voltage()
590 void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on) in ssb_pmu_set_ldo_paref() argument
592 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu_set_ldo_paref()
610 chipco_set32(cc, SSB_CHIPCO_PMU_MINRES_MSK, 1 << ldo); in ssb_pmu_set_ldo_paref()
612 chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, ~(1 << ldo)); in ssb_pmu_set_ldo_paref()
613 chipco_read32(cc, SSB_CHIPCO_PMU_MINRES_MSK); //SPEC FIXME found via mmiotrace - dummy read? in ssb_pmu_set_ldo_paref()
619 static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc) in ssb_pmu_get_alp_clock_clk0() argument
624 crystalfreq = (chipco_read32(cc, SSB_CHIPCO_PMU_CTL) & in ssb_pmu_get_alp_clock_clk0()
631 u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc) in ssb_pmu_get_alp_clock() argument
633 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu_get_alp_clock()
637 return ssb_pmu_get_alp_clock_clk0(cc); in ssb_pmu_get_alp_clock()
639 dev_err(cc->dev->dev, "ERROR: PMU alp clock unknown for device %04X\n", in ssb_pmu_get_alp_clock()
645 u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc) in ssb_pmu_get_cpu_clock() argument
647 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu_get_cpu_clock()
654 dev_err(cc->dev->dev, "ERROR: PMU cpu clock unknown for device %04X\n", in ssb_pmu_get_cpu_clock()
660 u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc) in ssb_pmu_get_controlclock() argument
662 struct ssb_bus *bus = cc->dev->bus; in ssb_pmu_get_controlclock()
668 dev_err(cc->dev->dev, "ERROR: PMU controlclock unknown for device %04X\n", in ssb_pmu_get_controlclock()
674 void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid) in ssb_pmu_spuravoid_pllupdate() argument
678 switch (cc->dev->bus->chip_id) { in ssb_pmu_spuravoid_pllupdate()
680 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070); in ssb_pmu_spuravoid_pllupdate()
681 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a); in ssb_pmu_spuravoid_pllupdate()
682 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854); in ssb_pmu_spuravoid_pllupdate()
684 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828); in ssb_pmu_spuravoid_pllupdate()
686 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828); in ssb_pmu_spuravoid_pllupdate()
691 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11500008); in ssb_pmu_spuravoid_pllupdate()
692 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0C000C06); in ssb_pmu_spuravoid_pllupdate()
693 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x0F600a08); in ssb_pmu_spuravoid_pllupdate()
694 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000); in ssb_pmu_spuravoid_pllupdate()
695 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x2001E920); in ssb_pmu_spuravoid_pllupdate()
696 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888815); in ssb_pmu_spuravoid_pllupdate()
698 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100008); in ssb_pmu_spuravoid_pllupdate()
699 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0c000c06); in ssb_pmu_spuravoid_pllupdate()
700 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x03000a08); in ssb_pmu_spuravoid_pllupdate()
701 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000); in ssb_pmu_spuravoid_pllupdate()
702 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x200005c0); in ssb_pmu_spuravoid_pllupdate()
703 ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888855); in ssb_pmu_spuravoid_pllupdate()
708 dev_err(cc->dev->dev, in ssb_pmu_spuravoid_pllupdate()
710 cc->dev->bus->chip_id); in ssb_pmu_spuravoid_pllupdate()
714 chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl); in ssb_pmu_spuravoid_pllupdate()