Lines Matching +full:refclk +full:- +full:frequency
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
11 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
23 #include <linux/spi/spi-mem.h>
120 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
161 * struct qspi_platform_data - zynqmp qspi platform data structure
169 * struct zynqmp_qspi - Defines qspi driver instance
172 * @refclk: Pointer to the peripheral clock
194 struct clk *refclk; member
215 * zynqmp_gqspi_read - For GQSPI controller read operation
222 return readl_relaxed(xqspi->regs + offset); in zynqmp_gqspi_read()
226 * zynqmp_gqspi_write - For GQSPI controller write operation
234 writel_relaxed(val, (xqspi->regs + offset)); in zynqmp_gqspi_write()
238 * zynqmp_gqspi_selectslave - For selection of slave device
241 * @slavebus: To check which bus is selected- upper or lower
254 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER | in zynqmp_gqspi_selectslave()
258 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER; in zynqmp_gqspi_selectslave()
261 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER; in zynqmp_gqspi_selectslave()
264 dev_warn(instanceptr->dev, "Invalid slave select\n"); in zynqmp_gqspi_selectslave()
270 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER | in zynqmp_gqspi_selectslave()
274 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER; in zynqmp_gqspi_selectslave()
277 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER; in zynqmp_gqspi_selectslave()
280 dev_warn(instanceptr->dev, "Invalid slave bus\n"); in zynqmp_gqspi_selectslave()
294 clk_rate = clk_get_rate(xqspi->refclk); in zynqmp_qspi_set_tapdelay()
297 if (!xqspi->has_tapdelay) { in zynqmp_qspi_set_tapdelay()
335 * zynqmp_qspi_init_hw - Initialize the hardware
340 * - Master mode
341 * - TX threshold set to 1
342 * - RX threshold set to 1
343 * - Flash memory interface mode enabled
345 * - Disable and clear all the interrupts
346 * - Enable manual slave select
347 * - Enable manual start
348 * - Deselect all the chip select lines
349 * - Set the little endian mode of TX FIFO
350 * - Set clock phase
351 * - Set clock polarity and
352 * - Enable the QSPI controller
389 /* Clear pre-scalar by default */ in zynqmp_qspi_init_hw()
392 if (xqspi->ctlr->mode_bits & SPI_CPHA) in zynqmp_qspi_init_hw()
397 if (xqspi->ctlr->mode_bits & SPI_CPOL) in zynqmp_qspi_init_hw()
402 /* Set the clock frequency */ in zynqmp_qspi_init_hw()
403 clk_rate = clk_get_rate(xqspi->refclk); in zynqmp_qspi_init_hw()
406 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > xqspi->speed_hz) in zynqmp_qspi_init_hw()
414 /* Set the tapdelay for clock frequency */ in zynqmp_qspi_init_hw()
442 * zynqmp_qspi_copy_read_data - Copy data to RX buffer
450 memcpy(xqspi->rxbuf, &data, size); in zynqmp_qspi_copy_read_data()
451 xqspi->rxbuf += size; in zynqmp_qspi_copy_read_data()
452 xqspi->bytes_to_receive -= size; in zynqmp_qspi_copy_read_data()
456 * zynqmp_qspi_chipselect - Select or deselect the chip select line
462 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master); in zynqmp_qspi_chipselect()
470 xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER; in zynqmp_qspi_chipselect()
471 xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER; in zynqmp_qspi_chipselect()
473 xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER; in zynqmp_qspi_chipselect()
474 xqspi->genfifocs = GQSPI_GENFIFO_CS_UPPER; in zynqmp_qspi_chipselect()
476 genfifoentry |= xqspi->genfifobus; in zynqmp_qspi_chipselect()
477 genfifoentry |= xqspi->genfifocs; in zynqmp_qspi_chipselect()
503 dev_err(xqspi->dev, "Chip select timed out\n"); in zynqmp_qspi_chipselect()
507 * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4.
509 * @spimode: spimode - SPI or DUAL or QUAD.
528 dev_warn(xqspi->dev, "Invalid SPI mode\n"); in zynqmp_qspi_selectspimode()
535 * zynqmp_qspi_config_op - Configure QSPI controller for specified
541 * sets the requested clock frequency.
546 * If the requested frequency is not an exact match with what can be
547 * obtained using the pre-scalar value, the driver sets the clock
548 * frequency which is lower than the requested frequency (maximum lower)
551 * If the requested frequency is higher or lower than that is supported
553 * frequency supported by controller.
561 req_speed_hz = qspi->max_speed_hz; in zynqmp_qspi_config_op()
563 if (xqspi->speed_hz != req_speed_hz) { in zynqmp_qspi_config_op()
564 xqspi->speed_hz = req_speed_hz; in zynqmp_qspi_config_op()
566 /* Set the clock frequency */ in zynqmp_qspi_config_op()
568 clk_rate = clk_get_rate(xqspi->refclk); in zynqmp_qspi_config_op()
587 * zynqmp_qspi_setup_op - Configure the QSPI controller
597 struct spi_controller *ctlr = qspi->master; in zynqmp_qspi_setup_op()
600 if (ctlr->busy) in zynqmp_qspi_setup_op()
601 return -EBUSY; in zynqmp_qspi_setup_op()
609 * zynqmp_qspi_filltxfifo - Fills the TX FIFO as long as there is room in
619 while ((xqspi->bytes_to_transfer > 0) && (count < size) && (xqspi->txbuf)) { in zynqmp_qspi_filltxfifo()
620 if (xqspi->bytes_to_transfer >= 4) { in zynqmp_qspi_filltxfifo()
621 memcpy(&intermediate, xqspi->txbuf, 4); in zynqmp_qspi_filltxfifo()
622 xqspi->txbuf += 4; in zynqmp_qspi_filltxfifo()
623 xqspi->bytes_to_transfer -= 4; in zynqmp_qspi_filltxfifo()
626 memcpy(&intermediate, xqspi->txbuf, in zynqmp_qspi_filltxfifo()
627 xqspi->bytes_to_transfer); in zynqmp_qspi_filltxfifo()
628 xqspi->txbuf += xqspi->bytes_to_transfer; in zynqmp_qspi_filltxfifo()
629 xqspi->bytes_to_transfer = 0; in zynqmp_qspi_filltxfifo()
630 count += xqspi->bytes_to_transfer; in zynqmp_qspi_filltxfifo()
637 * zynqmp_qspi_readrxfifo - Fills the RX FIFO as long as there is room in
647 while ((count < size) && (xqspi->bytes_to_receive > 0)) { in zynqmp_qspi_readrxfifo()
648 if (xqspi->bytes_to_receive >= 4) { in zynqmp_qspi_readrxfifo()
649 (*(u32 *)xqspi->rxbuf) = in zynqmp_qspi_readrxfifo()
651 xqspi->rxbuf += 4; in zynqmp_qspi_readrxfifo()
652 xqspi->bytes_to_receive -= 4; in zynqmp_qspi_readrxfifo()
656 count += xqspi->bytes_to_receive; in zynqmp_qspi_readrxfifo()
658 xqspi->bytes_to_receive); in zynqmp_qspi_readrxfifo()
659 xqspi->bytes_to_receive = 0; in zynqmp_qspi_readrxfifo()
665 * zynqmp_qspi_fillgenfifo - Fills the GENFIFO.
675 if (xqspi->txbuf) { in zynqmp_qspi_fillgenfifo()
679 transfer_len = xqspi->bytes_to_transfer; in zynqmp_qspi_fillgenfifo()
680 } else if (xqspi->rxbuf) { in zynqmp_qspi_fillgenfifo()
684 if (xqspi->mode == GQSPI_MODE_DMA) in zynqmp_qspi_fillgenfifo()
685 transfer_len = xqspi->dma_rx_bytes; in zynqmp_qspi_fillgenfifo()
687 transfer_len = xqspi->bytes_to_receive; in zynqmp_qspi_fillgenfifo()
692 transfer_len = xqspi->bytes_to_transfer; in zynqmp_qspi_fillgenfifo()
695 xqspi->genfifoentry = genfifoentry; in zynqmp_qspi_fillgenfifo()
732 if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf) { in zynqmp_qspi_fillgenfifo()
739 * zynqmp_process_dma_irq - Handler for DMA done interrupt of QSPI
749 dma_unmap_single(xqspi->dev, xqspi->dma_addr, in zynqmp_process_dma_irq()
750 xqspi->dma_rx_bytes, DMA_FROM_DEVICE); in zynqmp_process_dma_irq()
751 xqspi->rxbuf += xqspi->dma_rx_bytes; in zynqmp_process_dma_irq()
752 xqspi->bytes_to_receive -= xqspi->dma_rx_bytes; in zynqmp_process_dma_irq()
753 xqspi->dma_rx_bytes = 0; in zynqmp_process_dma_irq()
759 if (xqspi->bytes_to_receive > 0) { in zynqmp_process_dma_irq()
766 genfifoentry = xqspi->genfifoentry; in zynqmp_process_dma_irq()
767 genfifoentry |= xqspi->bytes_to_receive; in zynqmp_process_dma_irq()
788 * zynqmp_qspi_irq - Interrupt service routine of the QSPI controller
810 if (xqspi->mode == GQSPI_MODE_DMA) { in zynqmp_qspi_irq()
831 if (xqspi->bytes_to_receive == 0 && xqspi->bytes_to_transfer == 0 && in zynqmp_qspi_irq()
834 complete(&xqspi->data_completion); in zynqmp_qspi_irq()
841 * zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation
850 u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf; in zynqmp_qspi_setuprxdma()
852 if (xqspi->bytes_to_receive < 8 || in zynqmp_qspi_setuprxdma()
858 xqspi->mode = GQSPI_MODE_IO; in zynqmp_qspi_setuprxdma()
859 xqspi->dma_rx_bytes = 0; in zynqmp_qspi_setuprxdma()
863 rx_rem = xqspi->bytes_to_receive % 4; in zynqmp_qspi_setuprxdma()
864 rx_bytes = (xqspi->bytes_to_receive - rx_rem); in zynqmp_qspi_setuprxdma()
866 addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf, in zynqmp_qspi_setuprxdma()
868 if (dma_mapping_error(xqspi->dev, addr)) { in zynqmp_qspi_setuprxdma()
869 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n"); in zynqmp_qspi_setuprxdma()
870 return -ENOMEM; in zynqmp_qspi_setuprxdma()
873 xqspi->dma_rx_bytes = rx_bytes; in zynqmp_qspi_setuprxdma()
874 xqspi->dma_addr = addr; in zynqmp_qspi_setuprxdma()
888 xqspi->mode = GQSPI_MODE_DMA; in zynqmp_qspi_setuprxdma()
897 * zynqmp_qspi_write_op - This function sets up the GENFIFO entries,
912 if (xqspi->mode == GQSPI_MODE_DMA) { in zynqmp_qspi_write_op()
918 xqspi->mode = GQSPI_MODE_IO; in zynqmp_qspi_write_op()
923 * zynqmp_qspi_read_op - This function sets up the GENFIFO entries and
946 * zynqmp_qspi_suspend - Suspend method for the QSPI driver
956 struct spi_controller *ctlr = xqspi->ctlr; in zynqmp_qspi_suspend()
969 * zynqmp_qspi_resume - Resume method for the QSPI driver
980 struct spi_controller *ctlr = xqspi->ctlr; in zynqmp_qspi_resume()
990 * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
1001 clk_disable_unprepare(xqspi->refclk); in zynqmp_runtime_suspend()
1002 clk_disable_unprepare(xqspi->pclk); in zynqmp_runtime_suspend()
1008 * zynqmp_runtime_resume - Runtime resume method for the SPI driver
1020 ret = clk_prepare_enable(xqspi->pclk); in zynqmp_runtime_resume()
1026 ret = clk_prepare_enable(xqspi->refclk); in zynqmp_runtime_resume()
1029 clk_disable_unprepare(xqspi->pclk); in zynqmp_runtime_resume()
1037 * zynqmp_qspi_exec_op() - Initiates the QSPI transfer
1051 (mem->spi->master); in zynqmp_qspi_exec_op()
1054 u16 opcode = op->cmd.opcode; in zynqmp_qspi_exec_op()
1057 dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n", in zynqmp_qspi_exec_op()
1058 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, in zynqmp_qspi_exec_op()
1059 op->dummy.buswidth, op->data.buswidth); in zynqmp_qspi_exec_op()
1061 mutex_lock(&xqspi->op_lock); in zynqmp_qspi_exec_op()
1062 zynqmp_qspi_config_op(xqspi, mem->spi); in zynqmp_qspi_exec_op()
1063 zynqmp_qspi_chipselect(mem->spi, false); in zynqmp_qspi_exec_op()
1064 genfifoentry |= xqspi->genfifocs; in zynqmp_qspi_exec_op()
1065 genfifoentry |= xqspi->genfifobus; in zynqmp_qspi_exec_op()
1067 if (op->cmd.opcode) { in zynqmp_qspi_exec_op()
1068 reinit_completion(&xqspi->data_completion); in zynqmp_qspi_exec_op()
1069 xqspi->txbuf = &opcode; in zynqmp_qspi_exec_op()
1070 xqspi->rxbuf = NULL; in zynqmp_qspi_exec_op()
1071 xqspi->bytes_to_transfer = op->cmd.nbytes; in zynqmp_qspi_exec_op()
1072 xqspi->bytes_to_receive = 0; in zynqmp_qspi_exec_op()
1073 zynqmp_qspi_write_op(xqspi, op->cmd.buswidth, genfifoentry); in zynqmp_qspi_exec_op()
1081 (&xqspi->data_completion, msecs_to_jiffies(1000))) { in zynqmp_qspi_exec_op()
1082 err = -ETIMEDOUT; in zynqmp_qspi_exec_op()
1087 if (op->addr.nbytes) { in zynqmp_qspi_exec_op()
1088 xqspi->txbuf = &opaddr; in zynqmp_qspi_exec_op()
1089 for (i = 0; i < op->addr.nbytes; i++) { in zynqmp_qspi_exec_op()
1090 *(((u8 *)xqspi->txbuf) + i) = op->addr.val >> in zynqmp_qspi_exec_op()
1091 (8 * (op->addr.nbytes - i - 1)); in zynqmp_qspi_exec_op()
1094 reinit_completion(&xqspi->data_completion); in zynqmp_qspi_exec_op()
1095 xqspi->rxbuf = NULL; in zynqmp_qspi_exec_op()
1096 xqspi->bytes_to_transfer = op->addr.nbytes; in zynqmp_qspi_exec_op()
1097 xqspi->bytes_to_receive = 0; in zynqmp_qspi_exec_op()
1098 zynqmp_qspi_write_op(xqspi, op->addr.buswidth, genfifoentry); in zynqmp_qspi_exec_op()
1108 (&xqspi->data_completion, msecs_to_jiffies(1000))) { in zynqmp_qspi_exec_op()
1109 err = -ETIMEDOUT; in zynqmp_qspi_exec_op()
1114 if (op->dummy.nbytes) { in zynqmp_qspi_exec_op()
1115 xqspi->txbuf = NULL; in zynqmp_qspi_exec_op()
1116 xqspi->rxbuf = NULL; in zynqmp_qspi_exec_op()
1118 * xqspi->bytes_to_transfer here represents the dummy circles in zynqmp_qspi_exec_op()
1121 xqspi->bytes_to_transfer = op->dummy.nbytes * 8 / op->dummy.buswidth; in zynqmp_qspi_exec_op()
1122 xqspi->bytes_to_receive = 0; in zynqmp_qspi_exec_op()
1124 * Using op->data.buswidth instead of op->dummy.buswidth here because in zynqmp_qspi_exec_op()
1127 zynqmp_qspi_write_op(xqspi, op->data.buswidth, in zynqmp_qspi_exec_op()
1134 if (op->data.nbytes) { in zynqmp_qspi_exec_op()
1135 reinit_completion(&xqspi->data_completion); in zynqmp_qspi_exec_op()
1136 if (op->data.dir == SPI_MEM_DATA_OUT) { in zynqmp_qspi_exec_op()
1137 xqspi->txbuf = (u8 *)op->data.buf.out; in zynqmp_qspi_exec_op()
1138 xqspi->rxbuf = NULL; in zynqmp_qspi_exec_op()
1139 xqspi->bytes_to_transfer = op->data.nbytes; in zynqmp_qspi_exec_op()
1140 xqspi->bytes_to_receive = 0; in zynqmp_qspi_exec_op()
1141 zynqmp_qspi_write_op(xqspi, op->data.buswidth, in zynqmp_qspi_exec_op()
1152 xqspi->txbuf = NULL; in zynqmp_qspi_exec_op()
1153 xqspi->rxbuf = (u8 *)op->data.buf.in; in zynqmp_qspi_exec_op()
1154 xqspi->bytes_to_receive = op->data.nbytes; in zynqmp_qspi_exec_op()
1155 xqspi->bytes_to_transfer = 0; in zynqmp_qspi_exec_op()
1156 err = zynqmp_qspi_read_op(xqspi, op->data.buswidth, in zynqmp_qspi_exec_op()
1165 if (xqspi->mode == GQSPI_MODE_DMA) { in zynqmp_qspi_exec_op()
1177 (&xqspi->data_completion, msecs_to_jiffies(1000))) in zynqmp_qspi_exec_op()
1178 err = -ETIMEDOUT; in zynqmp_qspi_exec_op()
1183 zynqmp_qspi_chipselect(mem->spi, true); in zynqmp_qspi_exec_op()
1184 mutex_unlock(&xqspi->op_lock); in zynqmp_qspi_exec_op()
1200 { .compatible = "xlnx,zynqmp-qspi-1.0"},
1201 { .compatible = "xlnx,versal-qspi-1.0", .data = &versal_qspi_def },
1210 * zynqmp_qspi_probe - Probe method for the QSPI driver
1222 struct device *dev = &pdev->dev; in zynqmp_qspi_probe()
1223 struct device_node *np = dev->of_node; in zynqmp_qspi_probe()
1227 ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi)); in zynqmp_qspi_probe()
1229 return -ENOMEM; in zynqmp_qspi_probe()
1232 xqspi->dev = dev; in zynqmp_qspi_probe()
1233 xqspi->ctlr = ctlr; in zynqmp_qspi_probe()
1236 p_data = of_device_get_match_data(&pdev->dev); in zynqmp_qspi_probe()
1237 if (p_data && (p_data->quirks & QSPI_QUIRK_HAS_TAPDELAY)) in zynqmp_qspi_probe()
1238 xqspi->has_tapdelay = true; in zynqmp_qspi_probe()
1240 xqspi->regs = devm_platform_ioremap_resource(pdev, 0); in zynqmp_qspi_probe()
1241 if (IS_ERR(xqspi->regs)) { in zynqmp_qspi_probe()
1242 ret = PTR_ERR(xqspi->regs); in zynqmp_qspi_probe()
1246 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk"); in zynqmp_qspi_probe()
1247 if (IS_ERR(xqspi->pclk)) { in zynqmp_qspi_probe()
1249 ret = PTR_ERR(xqspi->pclk); in zynqmp_qspi_probe()
1253 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk"); in zynqmp_qspi_probe()
1254 if (IS_ERR(xqspi->refclk)) { in zynqmp_qspi_probe()
1256 ret = PTR_ERR(xqspi->refclk); in zynqmp_qspi_probe()
1260 ret = clk_prepare_enable(xqspi->pclk); in zynqmp_qspi_probe()
1266 ret = clk_prepare_enable(xqspi->refclk); in zynqmp_qspi_probe()
1272 init_completion(&xqspi->data_completion); in zynqmp_qspi_probe()
1274 mutex_init(&xqspi->op_lock); in zynqmp_qspi_probe()
1276 pm_runtime_use_autosuspend(&pdev->dev); in zynqmp_qspi_probe()
1277 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); in zynqmp_qspi_probe()
1278 pm_runtime_set_active(&pdev->dev); in zynqmp_qspi_probe()
1279 pm_runtime_enable(&pdev->dev); in zynqmp_qspi_probe()
1281 ret = pm_runtime_get_sync(&pdev->dev); in zynqmp_qspi_probe()
1283 dev_err(&pdev->dev, "Failed to pm_runtime_get_sync: %d\n", ret); in zynqmp_qspi_probe()
1287 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | in zynqmp_qspi_probe()
1289 ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2; in zynqmp_qspi_probe()
1290 xqspi->speed_hz = ctlr->max_speed_hz; in zynqmp_qspi_probe()
1295 xqspi->irq = platform_get_irq(pdev, 0); in zynqmp_qspi_probe()
1296 if (xqspi->irq < 0) { in zynqmp_qspi_probe()
1297 ret = xqspi->irq; in zynqmp_qspi_probe()
1300 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq, in zynqmp_qspi_probe()
1301 0, pdev->name, xqspi); in zynqmp_qspi_probe()
1303 ret = -ENXIO; in zynqmp_qspi_probe()
1308 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(44)); in zynqmp_qspi_probe()
1312 ret = of_property_read_u32(np, "num-cs", &num_cs); in zynqmp_qspi_probe()
1314 ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS; in zynqmp_qspi_probe()
1316 ret = -EINVAL; in zynqmp_qspi_probe()
1317 dev_err(&pdev->dev, "only %d chip selects are available\n", in zynqmp_qspi_probe()
1321 ctlr->num_chipselect = num_cs; in zynqmp_qspi_probe()
1324 ctlr->bits_per_word_mask = SPI_BPW_MASK(8); in zynqmp_qspi_probe()
1325 ctlr->mem_ops = &zynqmp_qspi_mem_ops; in zynqmp_qspi_probe()
1326 ctlr->setup = zynqmp_qspi_setup_op; in zynqmp_qspi_probe()
1327 ctlr->bits_per_word_mask = SPI_BPW_MASK(8); in zynqmp_qspi_probe()
1328 ctlr->dev.of_node = np; in zynqmp_qspi_probe()
1329 ctlr->auto_runtime_pm = true; in zynqmp_qspi_probe()
1331 ret = devm_spi_register_controller(&pdev->dev, ctlr); in zynqmp_qspi_probe()
1333 dev_err(&pdev->dev, "spi_register_controller failed\n"); in zynqmp_qspi_probe()
1337 pm_runtime_mark_last_busy(&pdev->dev); in zynqmp_qspi_probe()
1338 pm_runtime_put_autosuspend(&pdev->dev); in zynqmp_qspi_probe()
1343 pm_runtime_disable(&pdev->dev); in zynqmp_qspi_probe()
1344 pm_runtime_dont_use_autosuspend(&pdev->dev); in zynqmp_qspi_probe()
1345 pm_runtime_put_noidle(&pdev->dev); in zynqmp_qspi_probe()
1346 pm_runtime_set_suspended(&pdev->dev); in zynqmp_qspi_probe()
1347 clk_disable_unprepare(xqspi->refclk); in zynqmp_qspi_probe()
1349 clk_disable_unprepare(xqspi->pclk); in zynqmp_qspi_probe()
1357 * zynqmp_qspi_remove - Remove method for the QSPI driver
1370 pm_runtime_get_sync(&pdev->dev); in zynqmp_qspi_remove()
1374 pm_runtime_disable(&pdev->dev); in zynqmp_qspi_remove()
1375 pm_runtime_dont_use_autosuspend(&pdev->dev); in zynqmp_qspi_remove()
1376 pm_runtime_put_noidle(&pdev->dev); in zynqmp_qspi_remove()
1377 pm_runtime_set_suspended(&pdev->dev); in zynqmp_qspi_remove()
1378 clk_disable_unprepare(xqspi->refclk); in zynqmp_qspi_remove()
1379 clk_disable_unprepare(xqspi->pclk); in zynqmp_qspi_remove()
1388 .name = "zynqmp-qspi",