Lines Matching refs:tqspi
233 static inline u32 tegra_qspi_readl(struct tegra_qspi *tqspi, unsigned long offset) in tegra_qspi_readl() argument
235 return readl(tqspi->base + offset); in tegra_qspi_readl()
238 static inline void tegra_qspi_writel(struct tegra_qspi *tqspi, u32 value, unsigned long offset) in tegra_qspi_writel() argument
240 writel(value, tqspi->base + offset); in tegra_qspi_writel()
244 readl(tqspi->base + QSPI_COMMAND1); in tegra_qspi_writel()
247 static void tegra_qspi_mask_clear_irq(struct tegra_qspi *tqspi) in tegra_qspi_mask_clear_irq() argument
252 value = tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS); in tegra_qspi_mask_clear_irq()
253 tegra_qspi_writel(tqspi, value, QSPI_TRANS_STATUS); in tegra_qspi_mask_clear_irq()
255 value = tegra_qspi_readl(tqspi, QSPI_INTR_MASK); in tegra_qspi_mask_clear_irq()
258 tegra_qspi_writel(tqspi, value, QSPI_INTR_MASK); in tegra_qspi_mask_clear_irq()
262 value = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS); in tegra_qspi_mask_clear_irq()
264 tegra_qspi_writel(tqspi, QSPI_ERR | QSPI_FIFO_ERROR, QSPI_FIFO_STATUS); in tegra_qspi_mask_clear_irq()
268 tegra_qspi_calculate_curr_xfer_param(struct tegra_qspi *tqspi, struct spi_transfer *t) in tegra_qspi_calculate_curr_xfer_param() argument
271 unsigned int remain_len = t->len - tqspi->cur_pos; in tegra_qspi_calculate_curr_xfer_param()
274 tqspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); in tegra_qspi_calculate_curr_xfer_param()
285 tqspi->is_packed = true; in tegra_qspi_calculate_curr_xfer_param()
286 tqspi->words_per_32bit = 32 / bits_per_word; in tegra_qspi_calculate_curr_xfer_param()
288 tqspi->is_packed = false; in tegra_qspi_calculate_curr_xfer_param()
289 tqspi->words_per_32bit = 1; in tegra_qspi_calculate_curr_xfer_param()
292 if (tqspi->is_packed) { in tegra_qspi_calculate_curr_xfer_param()
293 max_len = min(remain_len, tqspi->max_buf_size); in tegra_qspi_calculate_curr_xfer_param()
294 tqspi->curr_dma_words = max_len / tqspi->bytes_per_word; in tegra_qspi_calculate_curr_xfer_param()
297 max_word = (remain_len - 1) / tqspi->bytes_per_word + 1; in tegra_qspi_calculate_curr_xfer_param()
298 max_word = min(max_word, tqspi->max_buf_size / 4); in tegra_qspi_calculate_curr_xfer_param()
299 tqspi->curr_dma_words = max_word; in tegra_qspi_calculate_curr_xfer_param()
307 tegra_qspi_fill_tx_fifo_from_client_txbuf(struct tegra_qspi *tqspi, struct spi_transfer *t) in tegra_qspi_fill_tx_fifo_from_client_txbuf() argument
311 u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
314 fifo_status = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS); in tegra_qspi_fill_tx_fifo_from_client_txbuf()
317 if (tqspi->is_packed) { in tegra_qspi_fill_tx_fifo_from_client_txbuf()
318 fifo_words_left = tx_empty_count * tqspi->words_per_32bit; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
319 written_words = min(fifo_words_left, tqspi->curr_dma_words); in tegra_qspi_fill_tx_fifo_from_client_txbuf()
320 len = written_words * tqspi->bytes_per_word; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
327 tegra_qspi_writel(tqspi, x, QSPI_TX_FIFO); in tegra_qspi_fill_tx_fifo_from_client_txbuf()
330 tqspi->cur_tx_pos += written_words * tqspi->bytes_per_word; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
333 u8 bytes_per_word = tqspi->bytes_per_word; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
335 max_n_32bit = min(tqspi->curr_dma_words, tx_empty_count); in tegra_qspi_fill_tx_fifo_from_client_txbuf()
337 len = written_words * tqspi->bytes_per_word; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
338 if (len > t->len - tqspi->cur_pos) in tegra_qspi_fill_tx_fifo_from_client_txbuf()
339 len = t->len - tqspi->cur_pos; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
346 tegra_qspi_writel(tqspi, x, QSPI_TX_FIFO); in tegra_qspi_fill_tx_fifo_from_client_txbuf()
349 tqspi->cur_tx_pos += write_bytes; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
356 tegra_qspi_read_rx_fifo_to_client_rxbuf(struct tegra_qspi *tqspi, struct spi_transfer *t) in tegra_qspi_read_rx_fifo_to_client_rxbuf() argument
358 u8 *rx_buf = (u8 *)t->rx_buf + tqspi->cur_rx_pos; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
363 fifo_status = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS); in tegra_qspi_read_rx_fifo_to_client_rxbuf()
365 if (tqspi->is_packed) { in tegra_qspi_read_rx_fifo_to_client_rxbuf()
366 len = tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
368 x = tegra_qspi_readl(tqspi, QSPI_RX_FIFO); in tegra_qspi_read_rx_fifo_to_client_rxbuf()
374 read_words += tqspi->curr_dma_words; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
375 tqspi->cur_rx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
378 u8 bytes_per_word = tqspi->bytes_per_word; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
382 if (len > t->len - tqspi->cur_pos) in tegra_qspi_read_rx_fifo_to_client_rxbuf()
383 len = t->len - tqspi->cur_pos; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
386 x = tegra_qspi_readl(tqspi, QSPI_RX_FIFO) & rx_mask; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
393 tqspi->cur_rx_pos += read_bytes; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
400 tegra_qspi_copy_client_txbuf_to_qspi_txbuf(struct tegra_qspi *tqspi, struct spi_transfer *t) in tegra_qspi_copy_client_txbuf_to_qspi_txbuf() argument
402 dma_sync_single_for_cpu(tqspi->dev, tqspi->tx_dma_phys, in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
403 tqspi->dma_buf_size, DMA_TO_DEVICE); in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
413 if (tqspi->is_packed) { in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
414 tqspi->cur_tx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
416 u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
423 consume = tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
424 if (consume > t->len - tqspi->cur_pos) in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
425 consume = t->len - tqspi->cur_pos; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
427 for (count = 0; count < tqspi->curr_dma_words; count++) { in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
430 for (i = 0; consume && (i < tqspi->bytes_per_word); i++, consume--) in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
432 tqspi->tx_dma_buf[count] = x; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
435 tqspi->cur_tx_pos += write_bytes; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
438 dma_sync_single_for_device(tqspi->dev, tqspi->tx_dma_phys, in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
439 tqspi->dma_buf_size, DMA_TO_DEVICE); in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
443 tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf(struct tegra_qspi *tqspi, struct spi_transfer *t) in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf() argument
445 dma_sync_single_for_cpu(tqspi->dev, tqspi->rx_dma_phys, in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
446 tqspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
448 if (tqspi->is_packed) { in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
449 tqspi->cur_rx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
451 unsigned char *rx_buf = t->rx_buf + tqspi->cur_rx_pos; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
460 consume = tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
461 if (consume > t->len - tqspi->cur_pos) in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
462 consume = t->len - tqspi->cur_pos; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
464 for (count = 0; count < tqspi->curr_dma_words; count++) { in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
465 u32 x = tqspi->rx_dma_buf[count] & rx_mask; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
467 for (i = 0; consume && (i < tqspi->bytes_per_word); i++, consume--) in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
471 tqspi->cur_rx_pos += read_bytes; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
474 dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
475 tqspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
485 static int tegra_qspi_start_tx_dma(struct tegra_qspi *tqspi, struct spi_transfer *t, int len) in tegra_qspi_start_tx_dma() argument
489 reinit_completion(&tqspi->tx_dma_complete); in tegra_qspi_start_tx_dma()
491 if (tqspi->is_packed) in tegra_qspi_start_tx_dma()
494 tx_dma_phys = tqspi->tx_dma_phys; in tegra_qspi_start_tx_dma()
496 tqspi->tx_dma_desc = dmaengine_prep_slave_single(tqspi->tx_dma_chan, tx_dma_phys, in tegra_qspi_start_tx_dma()
500 if (!tqspi->tx_dma_desc) { in tegra_qspi_start_tx_dma()
501 dev_err(tqspi->dev, "Unable to get TX descriptor\n"); in tegra_qspi_start_tx_dma()
505 tqspi->tx_dma_desc->callback = tegra_qspi_dma_complete; in tegra_qspi_start_tx_dma()
506 tqspi->tx_dma_desc->callback_param = &tqspi->tx_dma_complete; in tegra_qspi_start_tx_dma()
507 dmaengine_submit(tqspi->tx_dma_desc); in tegra_qspi_start_tx_dma()
508 dma_async_issue_pending(tqspi->tx_dma_chan); in tegra_qspi_start_tx_dma()
513 static int tegra_qspi_start_rx_dma(struct tegra_qspi *tqspi, struct spi_transfer *t, int len) in tegra_qspi_start_rx_dma() argument
517 reinit_completion(&tqspi->rx_dma_complete); in tegra_qspi_start_rx_dma()
519 if (tqspi->is_packed) in tegra_qspi_start_rx_dma()
522 rx_dma_phys = tqspi->rx_dma_phys; in tegra_qspi_start_rx_dma()
524 tqspi->rx_dma_desc = dmaengine_prep_slave_single(tqspi->rx_dma_chan, rx_dma_phys, in tegra_qspi_start_rx_dma()
528 if (!tqspi->rx_dma_desc) { in tegra_qspi_start_rx_dma()
529 dev_err(tqspi->dev, "Unable to get RX descriptor\n"); in tegra_qspi_start_rx_dma()
533 tqspi->rx_dma_desc->callback = tegra_qspi_dma_complete; in tegra_qspi_start_rx_dma()
534 tqspi->rx_dma_desc->callback_param = &tqspi->rx_dma_complete; in tegra_qspi_start_rx_dma()
535 dmaengine_submit(tqspi->rx_dma_desc); in tegra_qspi_start_rx_dma()
536 dma_async_issue_pending(tqspi->rx_dma_chan); in tegra_qspi_start_rx_dma()
541 static int tegra_qspi_flush_fifos(struct tegra_qspi *tqspi, bool atomic) in tegra_qspi_flush_fifos() argument
543 void __iomem *addr = tqspi->base + QSPI_FIFO_STATUS; in tegra_qspi_flush_fifos()
546 val = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS); in tegra_qspi_flush_fifos()
551 tegra_qspi_writel(tqspi, val, QSPI_FIFO_STATUS); in tegra_qspi_flush_fifos()
563 static void tegra_qspi_unmask_irq(struct tegra_qspi *tqspi) in tegra_qspi_unmask_irq() argument
567 intr_mask = tegra_qspi_readl(tqspi, QSPI_INTR_MASK); in tegra_qspi_unmask_irq()
569 tegra_qspi_writel(tqspi, intr_mask, QSPI_INTR_MASK); in tegra_qspi_unmask_irq()
572 static int tegra_qspi_dma_map_xfer(struct tegra_qspi *tqspi, struct spi_transfer *t) in tegra_qspi_dma_map_xfer() argument
574 u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos; in tegra_qspi_dma_map_xfer()
575 u8 *rx_buf = (u8 *)t->rx_buf + tqspi->cur_rx_pos; in tegra_qspi_dma_map_xfer()
578 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; in tegra_qspi_dma_map_xfer()
581 t->tx_dma = dma_map_single(tqspi->dev, (void *)tx_buf, len, DMA_TO_DEVICE); in tegra_qspi_dma_map_xfer()
582 if (dma_mapping_error(tqspi->dev, t->tx_dma)) in tegra_qspi_dma_map_xfer()
587 t->rx_dma = dma_map_single(tqspi->dev, (void *)rx_buf, len, DMA_FROM_DEVICE); in tegra_qspi_dma_map_xfer()
588 if (dma_mapping_error(tqspi->dev, t->rx_dma)) { in tegra_qspi_dma_map_xfer()
589 dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); in tegra_qspi_dma_map_xfer()
597 static void tegra_qspi_dma_unmap_xfer(struct tegra_qspi *tqspi, struct spi_transfer *t) in tegra_qspi_dma_unmap_xfer() argument
601 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; in tegra_qspi_dma_unmap_xfer()
603 dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); in tegra_qspi_dma_unmap_xfer()
604 dma_unmap_single(tqspi->dev, t->rx_dma, len, DMA_FROM_DEVICE); in tegra_qspi_dma_unmap_xfer()
607 static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct spi_transfer *t) in tegra_qspi_start_dma_based_transfer() argument
615 if (tqspi->is_packed) { in tegra_qspi_start_dma_based_transfer()
616 ret = tegra_qspi_dma_map_xfer(tqspi, t); in tegra_qspi_start_dma_based_transfer()
621 val = QSPI_DMA_BLK_SET(tqspi->curr_dma_words - 1); in tegra_qspi_start_dma_based_transfer()
622 tegra_qspi_writel(tqspi, val, QSPI_DMA_BLK); in tegra_qspi_start_dma_based_transfer()
624 tegra_qspi_unmask_irq(tqspi); in tegra_qspi_start_dma_based_transfer()
626 if (tqspi->is_packed) in tegra_qspi_start_dma_based_transfer()
627 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; in tegra_qspi_start_dma_based_transfer()
629 len = tqspi->curr_dma_words * 4; in tegra_qspi_start_dma_based_transfer()
644 tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL); in tegra_qspi_start_dma_based_transfer()
645 tqspi->dma_control_reg = val; in tegra_qspi_start_dma_based_transfer()
648 if (tqspi->cur_direction & DATA_DIR_TX) { in tegra_qspi_start_dma_based_transfer()
649 dma_sconfig.dst_addr = tqspi->phys + QSPI_TX_FIFO; in tegra_qspi_start_dma_based_transfer()
652 ret = dmaengine_slave_config(tqspi->tx_dma_chan, &dma_sconfig); in tegra_qspi_start_dma_based_transfer()
654 dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); in tegra_qspi_start_dma_based_transfer()
658 tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t); in tegra_qspi_start_dma_based_transfer()
659 ret = tegra_qspi_start_tx_dma(tqspi, t, len); in tegra_qspi_start_dma_based_transfer()
661 dev_err(tqspi->dev, "failed to starting TX DMA: %d\n", ret); in tegra_qspi_start_dma_based_transfer()
666 if (tqspi->cur_direction & DATA_DIR_RX) { in tegra_qspi_start_dma_based_transfer()
667 dma_sconfig.src_addr = tqspi->phys + QSPI_RX_FIFO; in tegra_qspi_start_dma_based_transfer()
670 ret = dmaengine_slave_config(tqspi->rx_dma_chan, &dma_sconfig); in tegra_qspi_start_dma_based_transfer()
672 dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); in tegra_qspi_start_dma_based_transfer()
676 dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, in tegra_qspi_start_dma_based_transfer()
677 tqspi->dma_buf_size, in tegra_qspi_start_dma_based_transfer()
680 ret = tegra_qspi_start_rx_dma(tqspi, t, len); in tegra_qspi_start_dma_based_transfer()
682 dev_err(tqspi->dev, "failed to start RX DMA: %d\n", ret); in tegra_qspi_start_dma_based_transfer()
683 if (tqspi->cur_direction & DATA_DIR_TX) in tegra_qspi_start_dma_based_transfer()
684 dmaengine_terminate_all(tqspi->tx_dma_chan); in tegra_qspi_start_dma_based_transfer()
689 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1); in tegra_qspi_start_dma_based_transfer()
691 tqspi->is_curr_dma_xfer = true; in tegra_qspi_start_dma_based_transfer()
692 tqspi->dma_control_reg = val; in tegra_qspi_start_dma_based_transfer()
694 tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL); in tegra_qspi_start_dma_based_transfer()
722 static void tegra_qspi_deinit_dma(struct tegra_qspi *tqspi) in tegra_qspi_deinit_dma() argument
724 if (!tqspi->soc_data->has_dma) in tegra_qspi_deinit_dma()
727 if (tqspi->tx_dma_buf) { in tegra_qspi_deinit_dma()
728 dma_free_coherent(tqspi->dev, tqspi->dma_buf_size, in tegra_qspi_deinit_dma()
729 tqspi->tx_dma_buf, tqspi->tx_dma_phys); in tegra_qspi_deinit_dma()
730 tqspi->tx_dma_buf = NULL; in tegra_qspi_deinit_dma()
733 if (tqspi->tx_dma_chan) { in tegra_qspi_deinit_dma()
734 dma_release_channel(tqspi->tx_dma_chan); in tegra_qspi_deinit_dma()
735 tqspi->tx_dma_chan = NULL; in tegra_qspi_deinit_dma()
738 if (tqspi->rx_dma_buf) { in tegra_qspi_deinit_dma()
739 dma_free_coherent(tqspi->dev, tqspi->dma_buf_size, in tegra_qspi_deinit_dma()
740 tqspi->rx_dma_buf, tqspi->rx_dma_phys); in tegra_qspi_deinit_dma()
741 tqspi->rx_dma_buf = NULL; in tegra_qspi_deinit_dma()
744 if (tqspi->rx_dma_chan) { in tegra_qspi_deinit_dma()
745 dma_release_channel(tqspi->rx_dma_chan); in tegra_qspi_deinit_dma()
746 tqspi->rx_dma_chan = NULL; in tegra_qspi_deinit_dma()
750 static int tegra_qspi_init_dma(struct tegra_qspi *tqspi) in tegra_qspi_init_dma() argument
757 if (!tqspi->soc_data->has_dma) in tegra_qspi_init_dma()
760 dma_chan = dma_request_chan(tqspi->dev, "rx"); in tegra_qspi_init_dma()
766 tqspi->rx_dma_chan = dma_chan; in tegra_qspi_init_dma()
768 dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL); in tegra_qspi_init_dma()
774 tqspi->rx_dma_buf = dma_buf; in tegra_qspi_init_dma()
775 tqspi->rx_dma_phys = dma_phys; in tegra_qspi_init_dma()
777 dma_chan = dma_request_chan(tqspi->dev, "tx"); in tegra_qspi_init_dma()
783 tqspi->tx_dma_chan = dma_chan; in tegra_qspi_init_dma()
785 dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL); in tegra_qspi_init_dma()
791 tqspi->tx_dma_buf = dma_buf; in tegra_qspi_init_dma()
792 tqspi->tx_dma_phys = dma_phys; in tegra_qspi_init_dma()
793 tqspi->use_dma = true; in tegra_qspi_init_dma()
798 tegra_qspi_deinit_dma(tqspi); in tegra_qspi_init_dma()
801 dev_err(tqspi->dev, "cannot use DMA: %d\n", err); in tegra_qspi_init_dma()
802 dev_err(tqspi->dev, "falling back to PIO\n"); in tegra_qspi_init_dma()
812 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_setup_transfer_one() local
819 if (!has_acpi_companion(tqspi->dev) && speed != tqspi->cur_speed) { in tegra_qspi_setup_transfer_one()
820 clk_set_rate(tqspi->clk, speed); in tegra_qspi_setup_transfer_one()
821 tqspi->cur_speed = speed; in tegra_qspi_setup_transfer_one()
824 tqspi->cur_pos = 0; in tegra_qspi_setup_transfer_one()
825 tqspi->cur_rx_pos = 0; in tegra_qspi_setup_transfer_one()
826 tqspi->cur_tx_pos = 0; in tegra_qspi_setup_transfer_one()
827 tqspi->curr_xfer = t; in tegra_qspi_setup_transfer_one()
830 tegra_qspi_mask_clear_irq(tqspi); in tegra_qspi_setup_transfer_one()
832 command1 = tqspi->def_command1_reg; in tegra_qspi_setup_transfer_one()
847 tegra_qspi_writel(tqspi, command1, QSPI_COMMAND1); in tegra_qspi_setup_transfer_one()
856 if (command2 != tqspi->def_command2_reg) in tegra_qspi_setup_transfer_one()
857 tegra_qspi_writel(tqspi, command2, QSPI_COMMAND2); in tegra_qspi_setup_transfer_one()
860 command1 = tqspi->command1_reg; in tegra_qspi_setup_transfer_one()
873 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_start_transfer_one() local
878 total_fifo_words = tegra_qspi_calculate_curr_xfer_param(tqspi, t); in tegra_qspi_start_transfer_one()
881 if (tqspi->is_packed) in tegra_qspi_start_transfer_one()
883 tegra_qspi_writel(tqspi, command1, QSPI_COMMAND1); in tegra_qspi_start_transfer_one()
885 tqspi->cur_direction = 0; in tegra_qspi_start_transfer_one()
890 tqspi->cur_direction |= DATA_DIR_RX; in tegra_qspi_start_transfer_one()
896 tqspi->cur_direction |= DATA_DIR_TX; in tegra_qspi_start_transfer_one()
909 tqspi->command1_reg = command1; in tegra_qspi_start_transfer_one()
911 tegra_qspi_writel(tqspi, QSPI_NUM_DUMMY_CYCLE(tqspi->dummy_cycles), QSPI_MISC_REG); in tegra_qspi_start_transfer_one()
913 ret = tegra_qspi_flush_fifos(tqspi, false); in tegra_qspi_start_transfer_one()
917 if (tqspi->use_dma && total_fifo_words > QSPI_FIFO_DEPTH) in tegra_qspi_start_transfer_one()
918 ret = tegra_qspi_start_dma_based_transfer(tqspi, t); in tegra_qspi_start_transfer_one()
920 ret = tegra_qspi_start_cpu_based_transfer(tqspi, t); in tegra_qspi_start_transfer_one()
928 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_parse_cdata_dt() local
930 cdata = devm_kzalloc(tqspi->dev, sizeof(*cdata), GFP_KERNEL); in tegra_qspi_parse_cdata_dt()
944 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_setup() local
950 ret = pm_runtime_resume_and_get(tqspi->dev); in tegra_qspi_setup()
952 dev_err(tqspi->dev, "failed to get runtime PM: %d\n", ret); in tegra_qspi_setup()
960 spin_lock_irqsave(&tqspi->lock, flags); in tegra_qspi_setup()
963 val = tqspi->def_command1_reg; in tegra_qspi_setup()
970 tqspi->def_command1_reg = val; in tegra_qspi_setup()
971 tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); in tegra_qspi_setup()
973 spin_unlock_irqrestore(&tqspi->lock, flags); in tegra_qspi_setup()
975 pm_runtime_put(tqspi->dev); in tegra_qspi_setup()
980 static void tegra_qspi_dump_regs(struct tegra_qspi *tqspi) in tegra_qspi_dump_regs() argument
982 dev_dbg(tqspi->dev, "============ QSPI REGISTER DUMP ============\n"); in tegra_qspi_dump_regs()
983 dev_dbg(tqspi->dev, "Command1: 0x%08x | Command2: 0x%08x\n", in tegra_qspi_dump_regs()
984 tegra_qspi_readl(tqspi, QSPI_COMMAND1), in tegra_qspi_dump_regs()
985 tegra_qspi_readl(tqspi, QSPI_COMMAND2)); in tegra_qspi_dump_regs()
986 dev_dbg(tqspi->dev, "DMA_CTL: 0x%08x | DMA_BLK: 0x%08x\n", in tegra_qspi_dump_regs()
987 tegra_qspi_readl(tqspi, QSPI_DMA_CTL), in tegra_qspi_dump_regs()
988 tegra_qspi_readl(tqspi, QSPI_DMA_BLK)); in tegra_qspi_dump_regs()
989 dev_dbg(tqspi->dev, "INTR_MASK: 0x%08x | MISC: 0x%08x\n", in tegra_qspi_dump_regs()
990 tegra_qspi_readl(tqspi, QSPI_INTR_MASK), in tegra_qspi_dump_regs()
991 tegra_qspi_readl(tqspi, QSPI_MISC_REG)); in tegra_qspi_dump_regs()
992 dev_dbg(tqspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n", in tegra_qspi_dump_regs()
993 tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS), in tegra_qspi_dump_regs()
994 tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS)); in tegra_qspi_dump_regs()
997 static void tegra_qspi_handle_error(struct tegra_qspi *tqspi) in tegra_qspi_handle_error() argument
999 dev_err(tqspi->dev, "error in transfer, fifo status 0x%08x\n", tqspi->status_reg); in tegra_qspi_handle_error()
1000 tegra_qspi_dump_regs(tqspi); in tegra_qspi_handle_error()
1001 tegra_qspi_flush_fifos(tqspi, true); in tegra_qspi_handle_error()
1002 if (device_reset(tqspi->dev) < 0) in tegra_qspi_handle_error()
1003 dev_warn_once(tqspi->dev, "device reset failed\n"); in tegra_qspi_handle_error()
1008 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_transfer_end() local
1012 tqspi->command1_reg |= QSPI_CS_SW_VAL; in tegra_qspi_transfer_end()
1014 tqspi->command1_reg &= ~QSPI_CS_SW_VAL; in tegra_qspi_transfer_end()
1015 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1); in tegra_qspi_transfer_end()
1016 tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); in tegra_qspi_transfer_end()
1054 static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, in tegra_qspi_combined_seq_xfer() argument
1068 val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG); in tegra_qspi_combined_seq_xfer()
1070 if (tqspi->soc_data->supports_tpm) in tegra_qspi_combined_seq_xfer()
1076 tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG); in tegra_qspi_combined_seq_xfer()
1094 tegra_qspi_writel(tqspi, cmd_value, QSPI_CMB_SEQ_CMD); in tegra_qspi_combined_seq_xfer()
1095 tegra_qspi_writel(tqspi, address_value, in tegra_qspi_combined_seq_xfer()
1098 tegra_qspi_writel(tqspi, cmd_config, in tegra_qspi_combined_seq_xfer()
1100 tegra_qspi_writel(tqspi, addr_config, in tegra_qspi_combined_seq_xfer()
1103 reinit_completion(&tqspi->xfer_completion); in tegra_qspi_combined_seq_xfer()
1110 dev_err(tqspi->dev, "Failed to start transfer-one: %d\n", in tegra_qspi_combined_seq_xfer()
1117 (&tqspi->xfer_completion, in tegra_qspi_combined_seq_xfer()
1121 dev_err(tqspi->dev, "QSPI Transfer failed with timeout: %d\n", in tegra_qspi_combined_seq_xfer()
1123 if (tqspi->is_curr_dma_xfer && in tegra_qspi_combined_seq_xfer()
1124 (tqspi->cur_direction & DATA_DIR_TX)) in tegra_qspi_combined_seq_xfer()
1126 (tqspi->tx_dma_chan); in tegra_qspi_combined_seq_xfer()
1128 if (tqspi->is_curr_dma_xfer && in tegra_qspi_combined_seq_xfer()
1129 (tqspi->cur_direction & DATA_DIR_RX)) in tegra_qspi_combined_seq_xfer()
1131 (tqspi->rx_dma_chan); in tegra_qspi_combined_seq_xfer()
1134 if (!tqspi->is_curr_dma_xfer) { in tegra_qspi_combined_seq_xfer()
1136 (tqspi, in tegra_qspi_combined_seq_xfer()
1140 (tqspi, cmd1, in tegra_qspi_combined_seq_xfer()
1144 (tqspi, in tegra_qspi_combined_seq_xfer()
1147 tegra_qspi_writel(tqspi, dma_ctl, in tegra_qspi_combined_seq_xfer()
1152 if (device_reset(tqspi->dev) < 0) in tegra_qspi_combined_seq_xfer()
1153 dev_warn_once(tqspi->dev, in tegra_qspi_combined_seq_xfer()
1159 if (tqspi->tx_status || tqspi->rx_status) { in tegra_qspi_combined_seq_xfer()
1160 dev_err(tqspi->dev, "QSPI Transfer failed\n"); in tegra_qspi_combined_seq_xfer()
1161 tqspi->tx_status = 0; in tegra_qspi_combined_seq_xfer()
1162 tqspi->rx_status = 0; in tegra_qspi_combined_seq_xfer()
1190 static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi, in tegra_qspi_non_combined_seq_xfer() argument
1200 tqspi->tx_status = 0; in tegra_qspi_non_combined_seq_xfer()
1201 tqspi->rx_status = 0; in tegra_qspi_non_combined_seq_xfer()
1204 val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG); in tegra_qspi_non_combined_seq_xfer()
1206 if (tqspi->soc_data->supports_tpm) in tegra_qspi_non_combined_seq_xfer()
1208 tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG); in tegra_qspi_non_combined_seq_xfer()
1214 tqspi->dummy_cycles = 0; in tegra_qspi_non_combined_seq_xfer()
1229 tqspi->dummy_cycles = dummy_cycles; in tegra_qspi_non_combined_seq_xfer()
1236 reinit_completion(&tqspi->xfer_completion); in tegra_qspi_non_combined_seq_xfer()
1242 dev_err(tqspi->dev, "failed to start transfer: %d\n", ret); in tegra_qspi_non_combined_seq_xfer()
1246 ret = wait_for_completion_timeout(&tqspi->xfer_completion, in tegra_qspi_non_combined_seq_xfer()
1249 dev_err(tqspi->dev, "transfer timeout\n"); in tegra_qspi_non_combined_seq_xfer()
1250 if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_TX)) in tegra_qspi_non_combined_seq_xfer()
1251 dmaengine_terminate_all(tqspi->tx_dma_chan); in tegra_qspi_non_combined_seq_xfer()
1252 if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_RX)) in tegra_qspi_non_combined_seq_xfer()
1253 dmaengine_terminate_all(tqspi->rx_dma_chan); in tegra_qspi_non_combined_seq_xfer()
1254 tegra_qspi_handle_error(tqspi); in tegra_qspi_non_combined_seq_xfer()
1259 if (tqspi->tx_status || tqspi->rx_status) { in tegra_qspi_non_combined_seq_xfer()
1260 tegra_qspi_handle_error(tqspi); in tegra_qspi_non_combined_seq_xfer()
1294 static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi, in tegra_qspi_validate_cmb_seq() argument
1303 if (!tqspi->soc_data->cmb_xfer_capable || transfer_count != 3) in tegra_qspi_validate_cmb_seq()
1313 if (!tqspi->soc_data->has_dma && xfer->len > (QSPI_FIFO_DEPTH << 2)) in tegra_qspi_validate_cmb_seq()
1322 struct tegra_qspi *tqspi = spi_master_get_devdata(master); in tegra_qspi_transfer_one_message() local
1325 if (tegra_qspi_validate_cmb_seq(tqspi, msg)) in tegra_qspi_transfer_one_message()
1326 ret = tegra_qspi_combined_seq_xfer(tqspi, msg); in tegra_qspi_transfer_one_message()
1328 ret = tegra_qspi_non_combined_seq_xfer(tqspi, msg); in tegra_qspi_transfer_one_message()
1335 static irqreturn_t handle_cpu_based_xfer(struct tegra_qspi *tqspi) in handle_cpu_based_xfer() argument
1337 struct spi_transfer *t = tqspi->curr_xfer; in handle_cpu_based_xfer()
1340 spin_lock_irqsave(&tqspi->lock, flags); in handle_cpu_based_xfer()
1342 if (tqspi->tx_status || tqspi->rx_status) { in handle_cpu_based_xfer()
1343 tegra_qspi_handle_error(tqspi); in handle_cpu_based_xfer()
1344 complete(&tqspi->xfer_completion); in handle_cpu_based_xfer()
1348 if (tqspi->cur_direction & DATA_DIR_RX) in handle_cpu_based_xfer()
1349 tegra_qspi_read_rx_fifo_to_client_rxbuf(tqspi, t); in handle_cpu_based_xfer()
1351 if (tqspi->cur_direction & DATA_DIR_TX) in handle_cpu_based_xfer()
1352 tqspi->cur_pos = tqspi->cur_tx_pos; in handle_cpu_based_xfer()
1354 tqspi->cur_pos = tqspi->cur_rx_pos; in handle_cpu_based_xfer()
1356 if (tqspi->cur_pos == t->len) { in handle_cpu_based_xfer()
1357 complete(&tqspi->xfer_completion); in handle_cpu_based_xfer()
1361 tegra_qspi_calculate_curr_xfer_param(tqspi, t); in handle_cpu_based_xfer()
1362 tegra_qspi_start_cpu_based_transfer(tqspi, t); in handle_cpu_based_xfer()
1364 spin_unlock_irqrestore(&tqspi->lock, flags); in handle_cpu_based_xfer()
1368 static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi) in handle_dma_based_xfer() argument
1370 struct spi_transfer *t = tqspi->curr_xfer; in handle_dma_based_xfer()
1376 if (tqspi->cur_direction & DATA_DIR_TX) { in handle_dma_based_xfer()
1377 if (tqspi->tx_status) { in handle_dma_based_xfer()
1378 dmaengine_terminate_all(tqspi->tx_dma_chan); in handle_dma_based_xfer()
1382 &tqspi->tx_dma_complete, QSPI_DMA_TIMEOUT); in handle_dma_based_xfer()
1384 dmaengine_terminate_all(tqspi->tx_dma_chan); in handle_dma_based_xfer()
1385 dev_err(tqspi->dev, "failed TX DMA transfer\n"); in handle_dma_based_xfer()
1391 if (tqspi->cur_direction & DATA_DIR_RX) { in handle_dma_based_xfer()
1392 if (tqspi->rx_status) { in handle_dma_based_xfer()
1393 dmaengine_terminate_all(tqspi->rx_dma_chan); in handle_dma_based_xfer()
1397 &tqspi->rx_dma_complete, QSPI_DMA_TIMEOUT); in handle_dma_based_xfer()
1399 dmaengine_terminate_all(tqspi->rx_dma_chan); in handle_dma_based_xfer()
1400 dev_err(tqspi->dev, "failed RX DMA transfer\n"); in handle_dma_based_xfer()
1406 spin_lock_irqsave(&tqspi->lock, flags); in handle_dma_based_xfer()
1409 tegra_qspi_dma_unmap_xfer(tqspi, t); in handle_dma_based_xfer()
1410 tegra_qspi_handle_error(tqspi); in handle_dma_based_xfer()
1411 complete(&tqspi->xfer_completion); in handle_dma_based_xfer()
1415 if (tqspi->cur_direction & DATA_DIR_RX) in handle_dma_based_xfer()
1416 tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf(tqspi, t); in handle_dma_based_xfer()
1418 if (tqspi->cur_direction & DATA_DIR_TX) in handle_dma_based_xfer()
1419 tqspi->cur_pos = tqspi->cur_tx_pos; in handle_dma_based_xfer()
1421 tqspi->cur_pos = tqspi->cur_rx_pos; in handle_dma_based_xfer()
1423 if (tqspi->cur_pos == t->len) { in handle_dma_based_xfer()
1424 tegra_qspi_dma_unmap_xfer(tqspi, t); in handle_dma_based_xfer()
1425 complete(&tqspi->xfer_completion); in handle_dma_based_xfer()
1429 tegra_qspi_dma_unmap_xfer(tqspi, t); in handle_dma_based_xfer()
1432 total_fifo_words = tegra_qspi_calculate_curr_xfer_param(tqspi, t); in handle_dma_based_xfer()
1434 err = tegra_qspi_start_dma_based_transfer(tqspi, t); in handle_dma_based_xfer()
1436 err = tegra_qspi_start_cpu_based_transfer(tqspi, t); in handle_dma_based_xfer()
1439 spin_unlock_irqrestore(&tqspi->lock, flags); in handle_dma_based_xfer()
1445 struct tegra_qspi *tqspi = context_data; in tegra_qspi_isr_thread() local
1447 tqspi->status_reg = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS); in tegra_qspi_isr_thread()
1449 if (tqspi->cur_direction & DATA_DIR_TX) in tegra_qspi_isr_thread()
1450 tqspi->tx_status = tqspi->status_reg & (QSPI_TX_FIFO_UNF | QSPI_TX_FIFO_OVF); in tegra_qspi_isr_thread()
1452 if (tqspi->cur_direction & DATA_DIR_RX) in tegra_qspi_isr_thread()
1453 tqspi->rx_status = tqspi->status_reg & (QSPI_RX_FIFO_OVF | QSPI_RX_FIFO_UNF); in tegra_qspi_isr_thread()
1455 tegra_qspi_mask_clear_irq(tqspi); in tegra_qspi_isr_thread()
1457 if (!tqspi->is_curr_dma_xfer) in tegra_qspi_isr_thread()
1458 return handle_cpu_based_xfer(tqspi); in tegra_qspi_isr_thread()
1460 return handle_dma_based_xfer(tqspi); in tegra_qspi_isr_thread()
1537 struct tegra_qspi *tqspi; in tegra_qspi_probe() local
1542 master = devm_spi_alloc_master(&pdev->dev, sizeof(*tqspi)); in tegra_qspi_probe()
1547 tqspi = spi_master_get_devdata(master); in tegra_qspi_probe()
1562 tqspi->master = master; in tegra_qspi_probe()
1563 tqspi->dev = &pdev->dev; in tegra_qspi_probe()
1564 spin_lock_init(&tqspi->lock); in tegra_qspi_probe()
1566 tqspi->soc_data = device_get_match_data(&pdev->dev); in tegra_qspi_probe()
1567 master->num_chipselect = tqspi->soc_data->cs_count; in tegra_qspi_probe()
1568 tqspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r); in tegra_qspi_probe()
1569 if (IS_ERR(tqspi->base)) in tegra_qspi_probe()
1570 return PTR_ERR(tqspi->base); in tegra_qspi_probe()
1572 tqspi->phys = r->start; in tegra_qspi_probe()
1576 tqspi->irq = qspi_irq; in tegra_qspi_probe()
1578 if (!has_acpi_companion(tqspi->dev)) { in tegra_qspi_probe()
1579 tqspi->clk = devm_clk_get(&pdev->dev, "qspi"); in tegra_qspi_probe()
1580 if (IS_ERR(tqspi->clk)) { in tegra_qspi_probe()
1581 ret = PTR_ERR(tqspi->clk); in tegra_qspi_probe()
1588 tqspi->max_buf_size = QSPI_FIFO_DEPTH << 2; in tegra_qspi_probe()
1589 tqspi->dma_buf_size = DEFAULT_QSPI_DMA_BUF_LEN; in tegra_qspi_probe()
1591 ret = tegra_qspi_init_dma(tqspi); in tegra_qspi_probe()
1595 if (tqspi->use_dma) in tegra_qspi_probe()
1596 tqspi->max_buf_size = tqspi->dma_buf_size; in tegra_qspi_probe()
1598 init_completion(&tqspi->tx_dma_complete); in tegra_qspi_probe()
1599 init_completion(&tqspi->rx_dma_complete); in tegra_qspi_probe()
1600 init_completion(&tqspi->xfer_completion); in tegra_qspi_probe()
1609 if (device_reset(tqspi->dev) < 0) in tegra_qspi_probe()
1610 dev_warn_once(tqspi->dev, "device reset failed\n"); in tegra_qspi_probe()
1612 tqspi->def_command1_reg = QSPI_M_S | QSPI_CS_SW_HW | QSPI_CS_SW_VAL; in tegra_qspi_probe()
1613 tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); in tegra_qspi_probe()
1614 tqspi->spi_cs_timing1 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING1); in tegra_qspi_probe()
1615 tqspi->spi_cs_timing2 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING2); in tegra_qspi_probe()
1616 tqspi->def_command2_reg = tegra_qspi_readl(tqspi, QSPI_COMMAND2); in tegra_qspi_probe()
1620 ret = request_threaded_irq(tqspi->irq, NULL, in tegra_qspi_probe()
1622 dev_name(&pdev->dev), tqspi); in tegra_qspi_probe()
1624 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", tqspi->irq, ret); in tegra_qspi_probe()
1638 free_irq(qspi_irq, tqspi); in tegra_qspi_probe()
1641 tegra_qspi_deinit_dma(tqspi); in tegra_qspi_probe()
1648 struct tegra_qspi *tqspi = spi_master_get_devdata(master); in tegra_qspi_remove() local
1651 free_irq(tqspi->irq, tqspi); in tegra_qspi_remove()
1653 tegra_qspi_deinit_dma(tqspi); in tegra_qspi_remove()
1666 struct tegra_qspi *tqspi = spi_master_get_devdata(master); in tegra_qspi_resume() local
1675 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1); in tegra_qspi_resume()
1676 tegra_qspi_writel(tqspi, tqspi->def_command2_reg, QSPI_COMMAND2); in tegra_qspi_resume()
1685 struct tegra_qspi *tqspi = spi_master_get_devdata(master); in tegra_qspi_runtime_suspend() local
1688 if (has_acpi_companion(tqspi->dev)) in tegra_qspi_runtime_suspend()
1691 tegra_qspi_readl(tqspi, QSPI_COMMAND1); in tegra_qspi_runtime_suspend()
1693 clk_disable_unprepare(tqspi->clk); in tegra_qspi_runtime_suspend()
1701 struct tegra_qspi *tqspi = spi_master_get_devdata(master); in tegra_qspi_runtime_resume() local
1705 if (has_acpi_companion(tqspi->dev)) in tegra_qspi_runtime_resume()
1707 ret = clk_prepare_enable(tqspi->clk); in tegra_qspi_runtime_resume()
1709 dev_err(tqspi->dev, "failed to enable clock: %d\n", ret); in tegra_qspi_runtime_resume()