Lines Matching +full:sun4i +full:- +full:a10 +full:- +full:spi
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012 - 2014 Allwinner Tech
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
19 #include <linux/spi/spi.h>
92 return readl(sspi->base_addr + reg); in sun4i_spi_read()
97 writel(value, sspi->base_addr + reg); in sun4i_spi_write()
138 while (len--) { in sun4i_spi_drain_fifo()
139 byte = readb(sspi->base_addr + SUN4I_RXDATA_REG); in sun4i_spi_drain_fifo()
140 if (sspi->rx_buf) in sun4i_spi_drain_fifo()
141 *sspi->rx_buf++ = byte; in sun4i_spi_drain_fifo()
151 cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi); in sun4i_spi_fill_fifo()
153 len = min3(len, (int)cnt, sspi->len); in sun4i_spi_fill_fifo()
155 while (len--) { in sun4i_spi_fill_fifo()
156 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; in sun4i_spi_fill_fifo()
157 writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG); in sun4i_spi_fill_fifo()
158 sspi->len--; in sun4i_spi_fill_fifo()
162 static void sun4i_spi_set_cs(struct spi_device *spi, bool enable) in sun4i_spi_set_cs() argument
164 struct sun4i_spi *sspi = spi_master_get_devdata(spi->master); in sun4i_spi_set_cs()
170 reg |= SUN4I_CTL_CS(spi_get_chipselect(spi, 0)); in sun4i_spi_set_cs()
191 if (spi->mode & SPI_CS_HIGH) in sun4i_spi_set_cs()
199 static size_t sun4i_spi_max_transfer_size(struct spi_device *spi) in sun4i_spi_max_transfer_size() argument
201 return SUN4I_MAX_XFER_SIZE - 1; in sun4i_spi_max_transfer_size()
205 struct spi_device *spi, in sun4i_spi_transfer_one() argument
216 if (tfr->len > SUN4I_MAX_XFER_SIZE) in sun4i_spi_transfer_one()
217 return -EMSGSIZE; in sun4i_spi_transfer_one()
219 if (tfr->tx_buf && tfr->len >= SUN4I_MAX_XFER_SIZE) in sun4i_spi_transfer_one()
220 return -EMSGSIZE; in sun4i_spi_transfer_one()
222 reinit_completion(&sspi->done); in sun4i_spi_transfer_one()
223 sspi->tx_buf = tfr->tx_buf; in sun4i_spi_transfer_one()
224 sspi->rx_buf = tfr->rx_buf; in sun4i_spi_transfer_one()
225 sspi->len = tfr->len; in sun4i_spi_transfer_one()
241 if (spi->mode & SPI_CPOL) in sun4i_spi_transfer_one()
246 if (spi->mode & SPI_CPHA) in sun4i_spi_transfer_one()
251 if (spi->mode & SPI_LSB_FIRST) in sun4i_spi_transfer_one()
261 if (sspi->rx_buf) in sun4i_spi_transfer_one()
269 mclk_rate = clk_get_rate(sspi->mclk); in sun4i_spi_transfer_one()
270 if (mclk_rate < (2 * tfr->speed_hz)) { in sun4i_spi_transfer_one()
271 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); in sun4i_spi_transfer_one()
272 mclk_rate = clk_get_rate(sspi->mclk); in sun4i_spi_transfer_one()
289 div = mclk_rate / (2 * tfr->speed_hz); in sun4i_spi_transfer_one()
292 div--; in sun4i_spi_transfer_one()
296 div = ilog2(mclk_rate) - ilog2(tfr->speed_hz); in sun4i_spi_transfer_one()
303 if (sspi->tx_buf) in sun4i_spi_transfer_one()
304 tx_len = tfr->len; in sun4i_spi_transfer_one()
307 sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len)); in sun4i_spi_transfer_one()
315 sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1); in sun4i_spi_transfer_one()
328 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); in sun4i_spi_transfer_one()
330 timeout = wait_for_completion_timeout(&sspi->done, in sun4i_spi_transfer_one()
334 dev_warn(&master->dev, in sun4i_spi_transfer_one()
336 dev_name(&spi->dev), tfr->len, tfr->speed_hz, in sun4i_spi_transfer_one()
337 jiffies_to_msecs(end - start), tx_time); in sun4i_spi_transfer_one()
338 ret = -ETIMEDOUT; in sun4i_spi_transfer_one()
358 complete(&sspi->done); in sun4i_spi_handler()
374 if (!sspi->len) in sun4i_spi_handler()
378 /* Only clear the interrupt _after_ re-seeding the FIFO */ in sun4i_spi_handler()
393 ret = clk_prepare_enable(sspi->hclk); in sun4i_spi_runtime_resume()
399 ret = clk_prepare_enable(sspi->mclk); in sun4i_spi_runtime_resume()
411 clk_disable_unprepare(sspi->hclk); in sun4i_spi_runtime_resume()
421 clk_disable_unprepare(sspi->mclk); in sun4i_spi_runtime_suspend()
422 clk_disable_unprepare(sspi->hclk); in sun4i_spi_runtime_suspend()
433 master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi)); in sun4i_spi_probe()
435 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); in sun4i_spi_probe()
436 return -ENOMEM; in sun4i_spi_probe()
442 sspi->base_addr = devm_platform_ioremap_resource(pdev, 0); in sun4i_spi_probe()
443 if (IS_ERR(sspi->base_addr)) { in sun4i_spi_probe()
444 ret = PTR_ERR(sspi->base_addr); in sun4i_spi_probe()
450 ret = -ENXIO; in sun4i_spi_probe()
454 ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler, in sun4i_spi_probe()
455 0, "sun4i-spi", sspi); in sun4i_spi_probe()
457 dev_err(&pdev->dev, "Cannot request IRQ\n"); in sun4i_spi_probe()
461 sspi->master = master; in sun4i_spi_probe()
462 master->max_speed_hz = 100 * 1000 * 1000; in sun4i_spi_probe()
463 master->min_speed_hz = 3 * 1000; in sun4i_spi_probe()
464 master->set_cs = sun4i_spi_set_cs; in sun4i_spi_probe()
465 master->transfer_one = sun4i_spi_transfer_one; in sun4i_spi_probe()
466 master->num_chipselect = 4; in sun4i_spi_probe()
467 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; in sun4i_spi_probe()
468 master->bits_per_word_mask = SPI_BPW_MASK(8); in sun4i_spi_probe()
469 master->dev.of_node = pdev->dev.of_node; in sun4i_spi_probe()
470 master->auto_runtime_pm = true; in sun4i_spi_probe()
471 master->max_transfer_size = sun4i_spi_max_transfer_size; in sun4i_spi_probe()
473 sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); in sun4i_spi_probe()
474 if (IS_ERR(sspi->hclk)) { in sun4i_spi_probe()
475 dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); in sun4i_spi_probe()
476 ret = PTR_ERR(sspi->hclk); in sun4i_spi_probe()
480 sspi->mclk = devm_clk_get(&pdev->dev, "mod"); in sun4i_spi_probe()
481 if (IS_ERR(sspi->mclk)) { in sun4i_spi_probe()
482 dev_err(&pdev->dev, "Unable to acquire module clock\n"); in sun4i_spi_probe()
483 ret = PTR_ERR(sspi->mclk); in sun4i_spi_probe()
487 init_completion(&sspi->done); in sun4i_spi_probe()
490 * This wake-up/shutdown pattern is to be able to have the in sun4i_spi_probe()
493 ret = sun4i_spi_runtime_resume(&pdev->dev); in sun4i_spi_probe()
495 dev_err(&pdev->dev, "Couldn't resume the device\n"); in sun4i_spi_probe()
499 pm_runtime_set_active(&pdev->dev); in sun4i_spi_probe()
500 pm_runtime_enable(&pdev->dev); in sun4i_spi_probe()
501 pm_runtime_idle(&pdev->dev); in sun4i_spi_probe()
503 ret = devm_spi_register_master(&pdev->dev, master); in sun4i_spi_probe()
505 dev_err(&pdev->dev, "cannot register SPI master\n"); in sun4i_spi_probe()
512 pm_runtime_disable(&pdev->dev); in sun4i_spi_probe()
513 sun4i_spi_runtime_suspend(&pdev->dev); in sun4i_spi_probe()
521 pm_runtime_force_suspend(&pdev->dev); in sun4i_spi_remove()
525 { .compatible = "allwinner,sun4i-a10-spi", },
539 .name = "sun4i-spi",
547 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
548 MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver");