Lines Matching +full:rx +full:- +full:ctrl
1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
175 #define STM32_SPI_MASTER_MODE(stm32_spi) (!(stm32_spi)->device_mode)
176 #define STM32_SPI_DEVICE_MODE(stm32_spi) ((stm32_spi)->device_mode)
179 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
191 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
193 * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
200 * @rx: SPI RX data register
212 const struct stm32_spi_reg rx; member
219 * struct stm32_spi_cfg - stm32 compatible configuration data
233 * @dma_rx_cb: routine to call after DMA RX channel operation is complete
268 * struct stm32_spi - private data of the SPI controller
270 * @ctrl: controller interface
278 * @cur_midi: master inter-data idleness in ns
291 * @dma_rx: dma channel for RX transfer
297 struct spi_controller *ctrl; member
338 .rx = { STM32F4_SPI_DR },
358 .rx = { STM32H7_SPI_RXDR },
365 writel_relaxed(readl_relaxed(spi->base + offset) | bits, in stm32_spi_set_bits()
366 spi->base + offset); in stm32_spi_set_bits()
372 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, in stm32_spi_clr_bits()
373 spi->base + offset); in stm32_spi_clr_bits()
377 * stm32h7_spi_get_fifo_size - Return fifo size
385 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
389 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) in stm32h7_spi_get_fifo_size()
390 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_get_fifo_size()
394 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
396 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count); in stm32h7_spi_get_fifo_size()
402 * stm32f4_spi_get_bpw_mask - Return bits per word mask
407 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n"); in stm32f4_spi_get_bpw_mask()
412 * stm32h7_spi_get_bpw_mask - Return bits per word mask
420 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
424 * maximum data size of periperal instances is limited to 16-bit in stm32h7_spi_get_bpw_mask()
428 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_get_bpw_mask()
431 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
433 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); in stm32h7_spi_get_bpw_mask()
439 * stm32_spi_prepare_mbr - Determine baud rate divisor value
445 * Return baud rate divisor value in case of success or -EINVAL
452 /* Ensure spi->clk_rate is even */ in stm32_spi_prepare_mbr()
453 div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz); in stm32_spi_prepare_mbr()
456 * SPI framework set xfer->speed_hz to ctrl->max_speed_hz if in stm32_spi_prepare_mbr()
457 * xfer->speed_hz is greater than ctrl->max_speed_hz, and it returns in stm32_spi_prepare_mbr()
458 * an error when xfer->speed_hz is lower than ctrl->min_speed_hz, so in stm32_spi_prepare_mbr()
463 return -EINVAL; in stm32_spi_prepare_mbr()
466 if (div & (div - 1)) in stm32_spi_prepare_mbr()
469 mbrdiv = fls(div) - 1; in stm32_spi_prepare_mbr()
471 spi->cur_speed = spi->clk_rate / (1 << mbrdiv); in stm32_spi_prepare_mbr()
473 spi->cur_half_period = DIV_ROUND_CLOSEST(USEC_PER_SEC, 2 * spi->cur_speed); in stm32_spi_prepare_mbr()
475 return mbrdiv - 1; in stm32_spi_prepare_mbr()
479 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
488 packet = clamp(xfer_len, 1U, spi->fifo_size / 2); in stm32h7_spi_prepare_fthlv()
491 bpw = DIV_ROUND_UP(spi->cur_bpw, 8); in stm32h7_spi_prepare_fthlv()
496 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
504 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & in stm32f4_spi_write_tx()
506 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32f4_spi_write_tx()
508 if (spi->cur_bpw == 16) { in stm32f4_spi_write_tx()
509 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
511 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR); in stm32f4_spi_write_tx()
512 spi->tx_len -= sizeof(u16); in stm32f4_spi_write_tx()
514 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
516 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR); in stm32f4_spi_write_tx()
517 spi->tx_len -= sizeof(u8); in stm32f4_spi_write_tx()
521 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32f4_spi_write_tx()
525 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
533 while ((spi->tx_len > 0) && in stm32h7_spi_write_txfifo()
534 (readl_relaxed(spi->base + STM32H7_SPI_SR) & in stm32h7_spi_write_txfifo()
536 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32h7_spi_write_txfifo()
538 if (spi->tx_len >= sizeof(u32)) { in stm32h7_spi_write_txfifo()
539 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
541 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
542 spi->tx_len -= sizeof(u32); in stm32h7_spi_write_txfifo()
543 } else if (spi->tx_len >= sizeof(u16)) { in stm32h7_spi_write_txfifo()
544 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
546 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
547 spi->tx_len -= sizeof(u16); in stm32h7_spi_write_txfifo()
549 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
551 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
552 spi->tx_len -= sizeof(u8); in stm32h7_spi_write_txfifo()
556 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32h7_spi_write_txfifo()
560 * stm32f4_spi_read_rx - Read bytes from Receive Data Register
568 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & in stm32f4_spi_read_rx()
570 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32f4_spi_read_rx()
572 if (spi->cur_bpw == 16) { in stm32f4_spi_read_rx()
573 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
575 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_read_rx()
576 spi->rx_len -= sizeof(u16); in stm32f4_spi_read_rx()
578 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
580 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_read_rx()
581 spi->rx_len -= sizeof(u8); in stm32f4_spi_read_rx()
585 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len); in stm32f4_spi_read_rx()
589 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
597 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
600 while ((spi->rx_len > 0) && in stm32h7_spi_read_rxfifo()
604 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32h7_spi_read_rxfifo()
606 if ((spi->rx_len >= sizeof(u32)) || in stm32h7_spi_read_rxfifo()
608 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
610 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
611 spi->rx_len -= sizeof(u32); in stm32h7_spi_read_rxfifo()
612 } else if ((spi->rx_len >= sizeof(u16)) || in stm32h7_spi_read_rxfifo()
614 (rxplvl >= 2 || spi->cur_bpw > 8))) { in stm32h7_spi_read_rxfifo()
615 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
617 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
618 spi->rx_len -= sizeof(u16); in stm32h7_spi_read_rxfifo()
620 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
622 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
623 spi->rx_len -= sizeof(u8); in stm32h7_spi_read_rxfifo()
626 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
630 dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n", in stm32h7_spi_read_rxfifo()
631 __func__, spi->rx_len, sr); in stm32h7_spi_read_rxfifo()
635 * stm32_spi_enable - Enable SPI controller
640 dev_dbg(spi->dev, "enable controller\n"); in stm32_spi_enable()
642 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg, in stm32_spi_enable()
643 spi->cfg->regs->en.mask); in stm32_spi_enable()
647 * stm32f4_spi_disable - Disable SPI controller
655 dev_dbg(spi->dev, "disable controller\n"); in stm32f4_spi_disable()
657 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_disable()
659 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) & in stm32f4_spi_disable()
661 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_disable()
671 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR, in stm32f4_spi_disable()
674 dev_warn(spi->dev, "disabling condition timeout\n"); in stm32f4_spi_disable()
677 if (spi->cur_usedma && spi->dma_tx) in stm32f4_spi_disable()
678 dmaengine_terminate_async(spi->dma_tx); in stm32f4_spi_disable()
679 if (spi->cur_usedma && spi->dma_rx) in stm32f4_spi_disable()
680 dmaengine_terminate_async(spi->dma_rx); in stm32f4_spi_disable()
688 readl_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_disable()
689 readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_disable()
691 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_disable()
695 * stm32h7_spi_disable - Disable SPI controller
698 * RX-Fifo is flushed when SPI controller is disabled.
705 dev_dbg(spi->dev, "disable controller\n"); in stm32h7_spi_disable()
707 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_disable()
709 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); in stm32h7_spi_disable()
712 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
717 if (spi->cur_half_period) in stm32h7_spi_disable()
718 udelay(spi->cur_half_period); in stm32h7_spi_disable()
720 if (spi->cur_usedma && spi->dma_tx) in stm32h7_spi_disable()
721 dmaengine_terminate_async(spi->dma_tx); in stm32h7_spi_disable()
722 if (spi->cur_usedma && spi->dma_rx) in stm32h7_spi_disable()
723 dmaengine_terminate_async(spi->dma_rx); in stm32h7_spi_disable()
731 writel_relaxed(0, spi->base + STM32H7_SPI_IER); in stm32h7_spi_disable()
732 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_disable()
734 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
738 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
739 * @ctrl: controller interface
746 static bool stm32_spi_can_dma(struct spi_controller *ctrl, in stm32_spi_can_dma() argument
751 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_can_dma()
753 if (spi->cfg->has_fifo) in stm32_spi_can_dma()
754 dma_size = spi->fifo_size; in stm32_spi_can_dma()
758 dev_dbg(spi->dev, "%s: %s\n", __func__, in stm32_spi_can_dma()
759 (transfer->len > dma_size) ? "true" : "false"); in stm32_spi_can_dma()
761 return (transfer->len > dma_size); in stm32_spi_can_dma()
765 * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
767 * @dev_id: SPI controller ctrl interface
771 struct spi_controller *ctrl = dev_id; in stm32f4_spi_irq_event() local
772 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32f4_spi_irq_event()
776 spin_lock(&spi->lock); in stm32f4_spi_irq_event()
778 sr = readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_irq_event()
785 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX || in stm32f4_spi_irq_event()
786 spi->cur_comm == SPI_3WIRE_TX)) { in stm32f4_spi_irq_event()
792 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX || in stm32f4_spi_irq_event()
793 spi->cur_comm == SPI_SIMPLEX_RX || in stm32f4_spi_irq_event()
794 spi->cur_comm == SPI_3WIRE_RX)) { in stm32f4_spi_irq_event()
801 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr); in stm32f4_spi_irq_event()
802 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
807 dev_warn(spi->dev, "Overrun: received value discarded\n"); in stm32f4_spi_irq_event()
810 readl_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_irq_event()
811 readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_irq_event()
823 if (spi->tx_buf) in stm32f4_spi_irq_event()
825 if (spi->tx_len == 0) in stm32f4_spi_irq_event()
831 if (spi->rx_len == 0) in stm32f4_spi_irq_event()
833 else if (spi->tx_buf)/* Load data for discontinuous mode */ in stm32f4_spi_irq_event()
844 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
848 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
853 * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
859 struct spi_controller *ctrl = dev_id; in stm32f4_spi_irq_thread() local
860 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32f4_spi_irq_thread()
862 spi_finalize_current_transfer(ctrl); in stm32f4_spi_irq_thread()
869 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
875 struct spi_controller *ctrl = dev_id; in stm32h7_spi_irq_thread() local
876 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32h7_spi_irq_thread()
881 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_irq_thread()
883 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_irq_thread()
884 ier = readl_relaxed(spi->base + STM32H7_SPI_IER); in stm32h7_spi_irq_thread()
894 * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP in stm32h7_spi_irq_thread()
895 * are set. So in case of Full-Duplex, need to poll TXP and RXP event. in stm32h7_spi_irq_thread()
897 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma) in stm32h7_spi_irq_thread()
901 dev_vdbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", in stm32h7_spi_irq_thread()
903 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
913 dev_dbg_ratelimited(spi->dev, "Communication suspended\n"); in stm32h7_spi_irq_thread()
914 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
920 if (spi->cur_usedma) in stm32h7_spi_irq_thread()
925 dev_warn(spi->dev, "Mode fault: transfer aborted\n"); in stm32h7_spi_irq_thread()
930 dev_err(spi->dev, "Overrun: RX data lost\n"); in stm32h7_spi_irq_thread()
935 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
937 if (!spi->cur_usedma || in stm32h7_spi_irq_thread()
938 (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX)) in stm32h7_spi_irq_thread()
943 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0))) in stm32h7_spi_irq_thread()
947 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
950 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_irq_thread()
952 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
956 spi_finalize_current_transfer(ctrl); in stm32h7_spi_irq_thread()
963 * stm32_spi_prepare_msg - set up the controller to transfer a single message
964 * @ctrl: controller interface
967 static int stm32_spi_prepare_msg(struct spi_controller *ctrl, in stm32_spi_prepare_msg() argument
970 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_prepare_msg()
971 struct spi_device *spi_dev = msg->spi; in stm32_spi_prepare_msg()
972 struct device_node *np = spi_dev->dev.of_node; in stm32_spi_prepare_msg()
977 spi->cur_midi = 0; in stm32_spi_prepare_msg()
978 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi)) in stm32_spi_prepare_msg()
979 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi); in stm32_spi_prepare_msg()
981 if (spi_dev->mode & SPI_CPOL) in stm32_spi_prepare_msg()
982 setb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
984 clrb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
986 if (spi_dev->mode & SPI_CPHA) in stm32_spi_prepare_msg()
987 setb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
989 clrb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
991 if (spi_dev->mode & SPI_LSB_FIRST) in stm32_spi_prepare_msg()
992 setb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
994 clrb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
996 if (STM32_SPI_DEVICE_MODE(spi) && spi_dev->mode & SPI_CS_HIGH) in stm32_spi_prepare_msg()
997 setb |= spi->cfg->regs->cs_high.mask; in stm32_spi_prepare_msg()
999 clrb |= spi->cfg->regs->cs_high.mask; in stm32_spi_prepare_msg()
1001 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", in stm32_spi_prepare_msg()
1002 !!(spi_dev->mode & SPI_CPOL), in stm32_spi_prepare_msg()
1003 !!(spi_dev->mode & SPI_CPHA), in stm32_spi_prepare_msg()
1004 !!(spi_dev->mode & SPI_LSB_FIRST), in stm32_spi_prepare_msg()
1005 !!(spi_dev->mode & SPI_CS_HIGH)); in stm32_spi_prepare_msg()
1011 if (spi->cfg->set_number_of_data) { in stm32_spi_prepare_msg()
1014 ret = spi_split_transfers_maxwords(ctrl, msg, in stm32_spi_prepare_msg()
1021 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_prepare_msg()
1026 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) & in stm32_spi_prepare_msg()
1028 spi->base + spi->cfg->regs->cpol.reg); in stm32_spi_prepare_msg()
1030 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_prepare_msg()
1036 * stm32f4_spi_dma_tx_cb - dma callback
1045 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32f4_spi_dma_tx_cb()
1046 spi_finalize_current_transfer(spi->ctrl); in stm32f4_spi_dma_tx_cb()
1052 * stm32_spi_dma_rx_cb - dma callback
1055 * DMA callback is called when the transfer is complete for DMA RX channel.
1061 spi_finalize_current_transfer(spi->ctrl); in stm32_spi_dma_rx_cb()
1062 spi->cfg->disable(spi); in stm32_spi_dma_rx_cb()
1066 * stm32_spi_dma_config - configure dma slave channel depending on current
1079 if (spi->cur_bpw <= 8) in stm32_spi_dma_config()
1081 else if (spi->cur_bpw <= 16) in stm32_spi_dma_config()
1086 if (spi->cfg->has_fifo) { in stm32_spi_dma_config()
1088 if (spi->cur_fthlv == 2) in stm32_spi_dma_config()
1091 maxburst = spi->cur_fthlv; in stm32_spi_dma_config()
1097 dma_conf->direction = dir; in stm32_spi_dma_config()
1098 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */ in stm32_spi_dma_config()
1099 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg; in stm32_spi_dma_config()
1100 dma_conf->src_addr_width = buswidth; in stm32_spi_dma_config()
1101 dma_conf->src_maxburst = maxburst; in stm32_spi_dma_config()
1103 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1105 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */ in stm32_spi_dma_config()
1106 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg; in stm32_spi_dma_config()
1107 dma_conf->dst_addr_width = buswidth; in stm32_spi_dma_config()
1108 dma_conf->dst_maxburst = maxburst; in stm32_spi_dma_config()
1110 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1116 * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
1129 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32f4_spi_transfer_one_irq()
1131 } else if (spi->cur_comm == SPI_FULL_DUPLEX || in stm32f4_spi_transfer_one_irq()
1132 spi->cur_comm == SPI_SIMPLEX_RX || in stm32f4_spi_transfer_one_irq()
1133 spi->cur_comm == SPI_3WIRE_RX) { in stm32f4_spi_transfer_one_irq()
1134 /* In transmit-only mode, the OVR flag is set in the SR register in stm32f4_spi_transfer_one_irq()
1136 * interrupt only when rx buffer is available. in stm32f4_spi_transfer_one_irq()
1140 return -EINVAL; in stm32f4_spi_transfer_one_irq()
1143 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_transfer_one_irq()
1150 if (spi->tx_buf) in stm32f4_spi_transfer_one_irq()
1153 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_transfer_one_irq()
1159 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1172 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */ in stm32h7_spi_transfer_one_irq()
1174 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */ in stm32h7_spi_transfer_one_irq()
1176 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */ in stm32h7_spi_transfer_one_irq()
1183 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1188 if (spi->tx_buf) in stm32h7_spi_transfer_one_irq()
1194 writel_relaxed(ier, spi->base + STM32H7_SPI_IER); in stm32h7_spi_transfer_one_irq()
1196 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1202 * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
1208 /* In DMA mode end of transfer is handled by DMA TX or RX callback. */ in stm32f4_spi_transfer_one_dma_start()
1209 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX || in stm32f4_spi_transfer_one_dma_start()
1210 spi->cur_comm == SPI_FULL_DUPLEX) { in stm32f4_spi_transfer_one_dma_start()
1212 * In transmit-only mode, the OVR flag is set in the SR register in stm32f4_spi_transfer_one_dma_start()
1214 * interrupt only when rx buffer is available. in stm32f4_spi_transfer_one_dma_start()
1223 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1232 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) in stm32h7_spi_transfer_one_dma_start()
1244 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
1258 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1261 if (spi->rx_buf && spi->dma_rx) { in stm32_spi_transfer_one_dma()
1263 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); in stm32_spi_transfer_one_dma()
1265 /* Enable Rx DMA request */ in stm32_spi_transfer_one_dma()
1266 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1267 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1270 spi->dma_rx, xfer->rx_sg.sgl, in stm32_spi_transfer_one_dma()
1271 xfer->rx_sg.nents, in stm32_spi_transfer_one_dma()
1277 if (spi->tx_buf && spi->dma_tx) { in stm32_spi_transfer_one_dma()
1279 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf); in stm32_spi_transfer_one_dma()
1282 spi->dma_tx, xfer->tx_sg.sgl, in stm32_spi_transfer_one_dma()
1283 xfer->tx_sg.nents, in stm32_spi_transfer_one_dma()
1288 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) || in stm32_spi_transfer_one_dma()
1289 (spi->rx_buf && spi->dma_rx && !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1292 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1296 rx_dma_desc->callback = spi->cfg->dma_rx_cb; in stm32_spi_transfer_one_dma()
1297 rx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1300 dev_err(spi->dev, "Rx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1303 /* Enable Rx DMA channel */ in stm32_spi_transfer_one_dma()
1304 dma_async_issue_pending(spi->dma_rx); in stm32_spi_transfer_one_dma()
1308 if (spi->cur_comm == SPI_SIMPLEX_TX || in stm32_spi_transfer_one_dma()
1309 spi->cur_comm == SPI_3WIRE_TX) { in stm32_spi_transfer_one_dma()
1310 tx_dma_desc->callback = spi->cfg->dma_tx_cb; in stm32_spi_transfer_one_dma()
1311 tx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1315 dev_err(spi->dev, "Tx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1319 dma_async_issue_pending(spi->dma_tx); in stm32_spi_transfer_one_dma()
1322 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg, in stm32_spi_transfer_one_dma()
1323 spi->cfg->regs->dma_tx_en.mask); in stm32_spi_transfer_one_dma()
1326 spi->cfg->transfer_one_dma_start(spi); in stm32_spi_transfer_one_dma()
1328 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1333 if (spi->dma_rx) in stm32_spi_transfer_one_dma()
1334 dmaengine_terminate_sync(spi->dma_rx); in stm32_spi_transfer_one_dma()
1337 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1338 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1340 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1342 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n"); in stm32_spi_transfer_one_dma()
1344 spi->cur_usedma = false; in stm32_spi_transfer_one_dma()
1345 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one_dma()
1349 * stm32f4_spi_set_bpw - Configure bits per word
1354 if (spi->cur_bpw == 16) in stm32f4_spi_set_bpw()
1361 * stm32h7_spi_set_bpw - configure bits per word
1369 bpw = spi->cur_bpw - 1; in stm32h7_spi_set_bpw()
1374 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen); in stm32h7_spi_set_bpw()
1375 fthlv = spi->cur_fthlv - 1; in stm32h7_spi_set_bpw()
1381 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) & in stm32h7_spi_set_bpw()
1383 spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_set_bpw()
1387 * stm32_spi_set_mbr - Configure baud rate divisor in master mode
1395 clrb |= spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1396 setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1398 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) & in stm32_spi_set_mbr()
1400 spi->base + spi->cfg->regs->br.reg); in stm32_spi_set_mbr()
1404 * stm32_spi_communication_type - return transfer communication type
1413 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */ in stm32_spi_communication_type()
1415 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL in stm32_spi_communication_type()
1420 if (!transfer->tx_buf) in stm32_spi_communication_type()
1425 if (!transfer->tx_buf) in stm32_spi_communication_type()
1427 else if (!transfer->rx_buf) in stm32_spi_communication_type()
1435 * stm32f4_spi_set_mode - configure communication mode
1456 return -EINVAL; in stm32f4_spi_set_mode()
1463 * stm32h7_spi_set_mode - configure communication mode
1490 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_set_mode()
1492 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_set_mode()
1498 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1508 if ((len > 1) && (spi->cur_midi > 0)) { in stm32h7_spi_data_idleness()
1509 u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed); in stm32h7_spi_data_idleness()
1511 DIV_ROUND_UP(spi->cur_midi, sck_period_ns), in stm32h7_spi_data_idleness()
1516 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", in stm32h7_spi_data_idleness()
1521 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_data_idleness()
1523 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_data_idleness()
1527 * stm32h7_spi_number_of_data - configure number of data at current transfer
1535 spi->base + STM32H7_SPI_CR2); in stm32h7_spi_number_of_data()
1537 return -EMSGSIZE; in stm32h7_spi_number_of_data()
1544 * stm32_spi_transfer_one_setup - common setup to transfer a single
1560 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1562 spi->cur_xferlen = transfer->len; in stm32_spi_transfer_one_setup()
1564 spi->cur_bpw = transfer->bits_per_word; in stm32_spi_transfer_one_setup()
1565 spi->cfg->set_bpw(spi); in stm32_spi_transfer_one_setup()
1567 /* Update spi->cur_speed with real clock speed */ in stm32_spi_transfer_one_setup()
1569 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz, in stm32_spi_transfer_one_setup()
1570 spi->cfg->baud_rate_div_min, in stm32_spi_transfer_one_setup()
1571 spi->cfg->baud_rate_div_max); in stm32_spi_transfer_one_setup()
1577 transfer->speed_hz = spi->cur_speed; in stm32_spi_transfer_one_setup()
1582 ret = spi->cfg->set_mode(spi, comm_type); in stm32_spi_transfer_one_setup()
1586 spi->cur_comm = comm_type; in stm32_spi_transfer_one_setup()
1588 if (STM32_SPI_MASTER_MODE(spi) && spi->cfg->set_data_idleness) in stm32_spi_transfer_one_setup()
1589 spi->cfg->set_data_idleness(spi, transfer->len); in stm32_spi_transfer_one_setup()
1591 if (spi->cur_bpw <= 8) in stm32_spi_transfer_one_setup()
1592 nb_words = transfer->len; in stm32_spi_transfer_one_setup()
1593 else if (spi->cur_bpw <= 16) in stm32_spi_transfer_one_setup()
1594 nb_words = DIV_ROUND_UP(transfer->len * 8, 16); in stm32_spi_transfer_one_setup()
1596 nb_words = DIV_ROUND_UP(transfer->len * 8, 32); in stm32_spi_transfer_one_setup()
1598 if (spi->cfg->set_number_of_data) { in stm32_spi_transfer_one_setup()
1599 ret = spi->cfg->set_number_of_data(spi, nb_words); in stm32_spi_transfer_one_setup()
1604 dev_dbg(spi->dev, "transfer communication mode set to %d\n", in stm32_spi_transfer_one_setup()
1605 spi->cur_comm); in stm32_spi_transfer_one_setup()
1606 dev_dbg(spi->dev, in stm32_spi_transfer_one_setup()
1607 "data frame of %d-bit, data packet of %d data frames\n", in stm32_spi_transfer_one_setup()
1608 spi->cur_bpw, spi->cur_fthlv); in stm32_spi_transfer_one_setup()
1610 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed); in stm32_spi_transfer_one_setup()
1611 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n", in stm32_spi_transfer_one_setup()
1612 spi->cur_xferlen, nb_words); in stm32_spi_transfer_one_setup()
1613 dev_dbg(spi->dev, "dma %s\n", in stm32_spi_transfer_one_setup()
1614 (spi->cur_usedma) ? "enabled" : "disabled"); in stm32_spi_transfer_one_setup()
1617 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1623 * stm32_spi_transfer_one - transfer a single spi_transfer
1624 * @ctrl: controller interface
1631 static int stm32_spi_transfer_one(struct spi_controller *ctrl, in stm32_spi_transfer_one() argument
1635 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_transfer_one()
1638 spi->tx_buf = transfer->tx_buf; in stm32_spi_transfer_one()
1639 spi->rx_buf = transfer->rx_buf; in stm32_spi_transfer_one()
1640 spi->tx_len = spi->tx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1641 spi->rx_len = spi->rx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1643 spi->cur_usedma = (ctrl->can_dma && in stm32_spi_transfer_one()
1644 ctrl->can_dma(ctrl, spi_dev, transfer)); in stm32_spi_transfer_one()
1648 dev_err(spi->dev, "SPI transfer setup failed\n"); in stm32_spi_transfer_one()
1652 if (spi->cur_usedma) in stm32_spi_transfer_one()
1655 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one()
1659 * stm32_spi_unprepare_msg - relax the hardware
1660 * @ctrl: controller interface
1663 static int stm32_spi_unprepare_msg(struct spi_controller *ctrl, in stm32_spi_unprepare_msg() argument
1666 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_unprepare_msg()
1668 spi->cfg->disable(spi); in stm32_spi_unprepare_msg()
1674 * stm32f4_spi_config - Configure SPI controller as SPI master
1681 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_config()
1688 * - SS input value high in stm32f4_spi_config()
1689 * - transmitter half duplex direction in stm32f4_spi_config()
1690 * - Set the master mode (default Motorola mode) in stm32f4_spi_config()
1691 * - Consider 1 master/n slaves configuration and in stm32f4_spi_config()
1699 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_config()
1705 * stm32h7_spi_config - Configure SPI controller
1713 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_config()
1724 * - Transmitter half duplex direction in stm32h7_spi_config()
1725 * - Automatic communication suspend when RX-Fifo is full in stm32h7_spi_config()
1726 * - SS input value high in stm32h7_spi_config()
1731 * - Set the master mode (default Motorola mode) in stm32h7_spi_config()
1732 * - Consider 1 master/n devices configuration and in stm32h7_spi_config()
1734 * - keep control of all associated GPIOs in stm32h7_spi_config()
1742 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_config()
1792 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1793 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1798 static int stm32h7_spi_device_abort(struct spi_controller *ctrl) in stm32h7_spi_device_abort() argument
1800 spi_finalize_current_transfer(ctrl); in stm32h7_spi_device_abort()
1806 struct spi_controller *ctrl; in stm32_spi_probe() local
1810 struct device_node *np = pdev->dev.of_node; in stm32_spi_probe()
1813 const struct stm32_spi_cfg *cfg = of_device_get_match_data(&pdev->dev); in stm32_spi_probe()
1815 device_mode = of_property_read_bool(np, "spi-slave"); in stm32_spi_probe()
1816 if (!cfg->has_device_mode && device_mode) { in stm32_spi_probe()
1817 dev_err(&pdev->dev, "spi-slave not supported\n"); in stm32_spi_probe()
1818 return -EPERM; in stm32_spi_probe()
1822 ctrl = devm_spi_alloc_slave(&pdev->dev, sizeof(struct stm32_spi)); in stm32_spi_probe()
1824 ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi)); in stm32_spi_probe()
1825 if (!ctrl) { in stm32_spi_probe()
1826 dev_err(&pdev->dev, "spi controller allocation failed\n"); in stm32_spi_probe()
1827 return -ENOMEM; in stm32_spi_probe()
1829 platform_set_drvdata(pdev, ctrl); in stm32_spi_probe()
1831 spi = spi_controller_get_devdata(ctrl); in stm32_spi_probe()
1832 spi->dev = &pdev->dev; in stm32_spi_probe()
1833 spi->ctrl = ctrl; in stm32_spi_probe()
1834 spi->device_mode = device_mode; in stm32_spi_probe()
1835 spin_lock_init(&spi->lock); in stm32_spi_probe()
1837 spi->cfg = cfg; in stm32_spi_probe()
1839 spi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in stm32_spi_probe()
1840 if (IS_ERR(spi->base)) in stm32_spi_probe()
1841 return PTR_ERR(spi->base); in stm32_spi_probe()
1843 spi->phys_addr = (dma_addr_t)res->start; in stm32_spi_probe()
1845 spi->irq = platform_get_irq(pdev, 0); in stm32_spi_probe()
1846 if (spi->irq <= 0) in stm32_spi_probe()
1847 return spi->irq; in stm32_spi_probe()
1849 ret = devm_request_threaded_irq(&pdev->dev, spi->irq, in stm32_spi_probe()
1850 spi->cfg->irq_handler_event, in stm32_spi_probe()
1851 spi->cfg->irq_handler_thread, in stm32_spi_probe()
1852 IRQF_ONESHOT, pdev->name, ctrl); in stm32_spi_probe()
1854 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq, in stm32_spi_probe()
1859 spi->clk = devm_clk_get(&pdev->dev, NULL); in stm32_spi_probe()
1860 if (IS_ERR(spi->clk)) { in stm32_spi_probe()
1861 ret = PTR_ERR(spi->clk); in stm32_spi_probe()
1862 dev_err(&pdev->dev, "clk get failed: %d\n", ret); in stm32_spi_probe()
1866 ret = clk_prepare_enable(spi->clk); in stm32_spi_probe()
1868 dev_err(&pdev->dev, "clk enable failed: %d\n", ret); in stm32_spi_probe()
1871 spi->clk_rate = clk_get_rate(spi->clk); in stm32_spi_probe()
1872 if (!spi->clk_rate) { in stm32_spi_probe()
1873 dev_err(&pdev->dev, "clk rate = 0\n"); in stm32_spi_probe()
1874 ret = -EINVAL; in stm32_spi_probe()
1878 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); in stm32_spi_probe()
1881 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst), in stm32_spi_probe()
1891 if (spi->cfg->has_fifo) in stm32_spi_probe()
1892 spi->fifo_size = spi->cfg->get_fifo_size(spi); in stm32_spi_probe()
1894 ret = spi->cfg->config(spi); in stm32_spi_probe()
1896 dev_err(&pdev->dev, "controller configuration failed: %d\n", in stm32_spi_probe()
1901 ctrl->dev.of_node = pdev->dev.of_node; in stm32_spi_probe()
1902 ctrl->auto_runtime_pm = true; in stm32_spi_probe()
1903 ctrl->bus_num = pdev->id; in stm32_spi_probe()
1904 ctrl->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | in stm32_spi_probe()
1906 ctrl->bits_per_word_mask = spi->cfg->get_bpw_mask(spi); in stm32_spi_probe()
1907 ctrl->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min; in stm32_spi_probe()
1908 ctrl->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max; in stm32_spi_probe()
1909 ctrl->use_gpio_descriptors = true; in stm32_spi_probe()
1910 ctrl->prepare_message = stm32_spi_prepare_msg; in stm32_spi_probe()
1911 ctrl->transfer_one = stm32_spi_transfer_one; in stm32_spi_probe()
1912 ctrl->unprepare_message = stm32_spi_unprepare_msg; in stm32_spi_probe()
1913 ctrl->flags = spi->cfg->flags; in stm32_spi_probe()
1915 ctrl->slave_abort = stm32h7_spi_device_abort; in stm32_spi_probe()
1917 spi->dma_tx = dma_request_chan(spi->dev, "tx"); in stm32_spi_probe()
1918 if (IS_ERR(spi->dma_tx)) { in stm32_spi_probe()
1919 ret = PTR_ERR(spi->dma_tx); in stm32_spi_probe()
1920 spi->dma_tx = NULL; in stm32_spi_probe()
1921 if (ret == -EPROBE_DEFER) in stm32_spi_probe()
1924 dev_warn(&pdev->dev, "failed to request tx dma channel\n"); in stm32_spi_probe()
1926 ctrl->dma_tx = spi->dma_tx; in stm32_spi_probe()
1929 spi->dma_rx = dma_request_chan(spi->dev, "rx"); in stm32_spi_probe()
1930 if (IS_ERR(spi->dma_rx)) { in stm32_spi_probe()
1931 ret = PTR_ERR(spi->dma_rx); in stm32_spi_probe()
1932 spi->dma_rx = NULL; in stm32_spi_probe()
1933 if (ret == -EPROBE_DEFER) in stm32_spi_probe()
1936 dev_warn(&pdev->dev, "failed to request rx dma channel\n"); in stm32_spi_probe()
1938 ctrl->dma_rx = spi->dma_rx; in stm32_spi_probe()
1941 if (spi->dma_tx || spi->dma_rx) in stm32_spi_probe()
1942 ctrl->can_dma = stm32_spi_can_dma; in stm32_spi_probe()
1944 pm_runtime_set_autosuspend_delay(&pdev->dev, in stm32_spi_probe()
1946 pm_runtime_use_autosuspend(&pdev->dev); in stm32_spi_probe()
1947 pm_runtime_set_active(&pdev->dev); in stm32_spi_probe()
1948 pm_runtime_get_noresume(&pdev->dev); in stm32_spi_probe()
1949 pm_runtime_enable(&pdev->dev); in stm32_spi_probe()
1951 ret = spi_register_controller(ctrl); in stm32_spi_probe()
1953 dev_err(&pdev->dev, "spi controller registration failed: %d\n", in stm32_spi_probe()
1958 pm_runtime_mark_last_busy(&pdev->dev); in stm32_spi_probe()
1959 pm_runtime_put_autosuspend(&pdev->dev); in stm32_spi_probe()
1961 dev_info(&pdev->dev, "driver initialized (%s mode)\n", in stm32_spi_probe()
1967 pm_runtime_disable(&pdev->dev); in stm32_spi_probe()
1968 pm_runtime_put_noidle(&pdev->dev); in stm32_spi_probe()
1969 pm_runtime_set_suspended(&pdev->dev); in stm32_spi_probe()
1970 pm_runtime_dont_use_autosuspend(&pdev->dev); in stm32_spi_probe()
1972 if (spi->dma_tx) in stm32_spi_probe()
1973 dma_release_channel(spi->dma_tx); in stm32_spi_probe()
1974 if (spi->dma_rx) in stm32_spi_probe()
1975 dma_release_channel(spi->dma_rx); in stm32_spi_probe()
1977 clk_disable_unprepare(spi->clk); in stm32_spi_probe()
1984 struct spi_controller *ctrl = platform_get_drvdata(pdev); in stm32_spi_remove() local
1985 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_remove()
1987 pm_runtime_get_sync(&pdev->dev); in stm32_spi_remove()
1989 spi_unregister_controller(ctrl); in stm32_spi_remove()
1990 spi->cfg->disable(spi); in stm32_spi_remove()
1992 pm_runtime_disable(&pdev->dev); in stm32_spi_remove()
1993 pm_runtime_put_noidle(&pdev->dev); in stm32_spi_remove()
1994 pm_runtime_set_suspended(&pdev->dev); in stm32_spi_remove()
1995 pm_runtime_dont_use_autosuspend(&pdev->dev); in stm32_spi_remove()
1997 if (ctrl->dma_tx) in stm32_spi_remove()
1998 dma_release_channel(ctrl->dma_tx); in stm32_spi_remove()
1999 if (ctrl->dma_rx) in stm32_spi_remove()
2000 dma_release_channel(ctrl->dma_rx); in stm32_spi_remove()
2002 clk_disable_unprepare(spi->clk); in stm32_spi_remove()
2005 pinctrl_pm_select_sleep_state(&pdev->dev); in stm32_spi_remove()
2010 struct spi_controller *ctrl = dev_get_drvdata(dev); in stm32_spi_runtime_suspend() local
2011 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_runtime_suspend()
2013 clk_disable_unprepare(spi->clk); in stm32_spi_runtime_suspend()
2020 struct spi_controller *ctrl = dev_get_drvdata(dev); in stm32_spi_runtime_resume() local
2021 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_runtime_resume()
2028 return clk_prepare_enable(spi->clk); in stm32_spi_runtime_resume()
2033 struct spi_controller *ctrl = dev_get_drvdata(dev); in stm32_spi_suspend() local
2036 ret = spi_controller_suspend(ctrl); in stm32_spi_suspend()
2045 struct spi_controller *ctrl = dev_get_drvdata(dev); in stm32_spi_resume() local
2046 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_resume()
2053 ret = spi_controller_resume(ctrl); in stm32_spi_resume()
2055 clk_disable_unprepare(spi->clk); in stm32_spi_resume()
2065 spi->cfg->config(spi); in stm32_spi_resume()