Lines Matching +full:csi +full:- +full:pclk
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Renesas RZ/V2M Clocked Serial Interface (CSI) driver
21 #define CSI_MODE 0x00 /* CSI mode control */
22 #define CSI_CLKSEL 0x04 /* CSI clock select */
23 #define CSI_CNT 0x08 /* CSI control */
24 #define CSI_INT 0x0C /* CSI interrupt status */
25 #define CSI_IFIFOL 0x10 /* CSI receive FIFO level display */
26 #define CSI_OFIFOL 0x14 /* CSI transmit FIFO level display */
27 #define CSI_IFIFO 0x18 /* CSI receive window */
28 #define CSI_OFIFO 0x1C /* CSI transmit window */
29 #define CSI_FIFOTRG 0x20 /* CSI FIFO trigger level */
88 struct clk *pclk; member
104 static void rzv2m_csi_reg_write_bit(const struct rzv2m_csi_priv *csi, in rzv2m_csi_reg_write_bit() argument
113 tmp = (readl(csi->base + reg_offs) & ~bit_mask) | value; in rzv2m_csi_reg_write_bit()
114 writel(tmp, csi->base + reg_offs); in rzv2m_csi_reg_write_bit()
117 static int rzv2m_csi_sw_reset(struct rzv2m_csi_priv *csi, int assert) in rzv2m_csi_sw_reset() argument
121 rzv2m_csi_reg_write_bit(csi, CSI_CNT, CSI_CNT_CSIRST, assert); in rzv2m_csi_sw_reset()
126 return readl_poll_timeout(csi->base + CSI_MODE, reg, in rzv2m_csi_sw_reset()
131 static int rzv2m_csi_start_stop_operation(const struct rzv2m_csi_priv *csi, in rzv2m_csi_start_stop_operation() argument
136 rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_CSIE, enable); in rzv2m_csi_start_stop_operation()
141 return readl_poll_timeout(csi->base + CSI_MODE, reg, in rzv2m_csi_start_stop_operation()
146 static int rzv2m_csi_fill_txfifo(struct rzv2m_csi_priv *csi) in rzv2m_csi_fill_txfifo() argument
150 if (readl(csi->base + CSI_OFIFOL)) in rzv2m_csi_fill_txfifo()
151 return -EIO; in rzv2m_csi_fill_txfifo()
153 if (csi->bytes_per_word == 2) { in rzv2m_csi_fill_txfifo()
154 const u16 *buf = csi->txbuf; in rzv2m_csi_fill_txfifo()
156 for (i = 0; i < csi->words_to_transfer; i++) in rzv2m_csi_fill_txfifo()
157 writel(buf[i], csi->base + CSI_OFIFO); in rzv2m_csi_fill_txfifo()
159 const u8 *buf = csi->txbuf; in rzv2m_csi_fill_txfifo()
161 for (i = 0; i < csi->words_to_transfer; i++) in rzv2m_csi_fill_txfifo()
162 writel(buf[i], csi->base + CSI_OFIFO); in rzv2m_csi_fill_txfifo()
165 csi->txbuf += csi->bytes_to_transfer; in rzv2m_csi_fill_txfifo()
166 csi->bytes_sent += csi->bytes_to_transfer; in rzv2m_csi_fill_txfifo()
171 static int rzv2m_csi_read_rxfifo(struct rzv2m_csi_priv *csi) in rzv2m_csi_read_rxfifo() argument
175 if (readl(csi->base + CSI_IFIFOL) != csi->bytes_to_transfer) in rzv2m_csi_read_rxfifo()
176 return -EIO; in rzv2m_csi_read_rxfifo()
178 if (csi->bytes_per_word == 2) { in rzv2m_csi_read_rxfifo()
179 u16 *buf = csi->rxbuf; in rzv2m_csi_read_rxfifo()
181 for (i = 0; i < csi->words_to_transfer; i++) in rzv2m_csi_read_rxfifo()
182 buf[i] = (u16)readl(csi->base + CSI_IFIFO); in rzv2m_csi_read_rxfifo()
184 u8 *buf = csi->rxbuf; in rzv2m_csi_read_rxfifo()
186 for (i = 0; i < csi->words_to_transfer; i++) in rzv2m_csi_read_rxfifo()
187 buf[i] = (u8)readl(csi->base + CSI_IFIFO); in rzv2m_csi_read_rxfifo()
190 csi->rxbuf += csi->bytes_to_transfer; in rzv2m_csi_read_rxfifo()
191 csi->bytes_received += csi->bytes_to_transfer; in rzv2m_csi_read_rxfifo()
196 static inline void rzv2m_csi_calc_current_transfer(struct rzv2m_csi_priv *csi) in rzv2m_csi_calc_current_transfer() argument
198 unsigned int bytes_transferred = max(csi->bytes_received, csi->bytes_sent); in rzv2m_csi_calc_current_transfer()
199 unsigned int bytes_remaining = csi->buffer_len - bytes_transferred; in rzv2m_csi_calc_current_transfer()
202 if (csi->txbuf) in rzv2m_csi_calc_current_transfer()
212 if (csi->bytes_per_word == 2) in rzv2m_csi_calc_current_transfer()
221 csi->words_to_transfer = rounddown_pow_of_two(to_transfer); in rzv2m_csi_calc_current_transfer()
223 if (csi->bytes_per_word == 2) in rzv2m_csi_calc_current_transfer()
224 csi->bytes_to_transfer = csi->words_to_transfer << 1; in rzv2m_csi_calc_current_transfer()
226 csi->bytes_to_transfer = csi->words_to_transfer; in rzv2m_csi_calc_current_transfer()
229 static inline void rzv2m_csi_set_rx_fifo_trigger_level(struct rzv2m_csi_priv *csi) in rzv2m_csi_set_rx_fifo_trigger_level() argument
231 rzv2m_csi_reg_write_bit(csi, CSI_FIFOTRG, CSI_FIFOTRG_R_TRG, in rzv2m_csi_set_rx_fifo_trigger_level()
232 ilog2(csi->words_to_transfer)); in rzv2m_csi_set_rx_fifo_trigger_level()
235 static inline void rzv2m_csi_enable_rx_trigger(struct rzv2m_csi_priv *csi, in rzv2m_csi_enable_rx_trigger() argument
238 rzv2m_csi_reg_write_bit(csi, CSI_CNT, CSI_CNT_R_TRGEN, enable); in rzv2m_csi_enable_rx_trigger()
241 static void rzv2m_csi_disable_irqs(const struct rzv2m_csi_priv *csi, in rzv2m_csi_disable_irqs() argument
244 u32 cnt = readl(csi->base + CSI_CNT); in rzv2m_csi_disable_irqs()
246 writel(cnt & ~enable_bits, csi->base + CSI_CNT); in rzv2m_csi_disable_irqs()
249 static void rzv2m_csi_disable_all_irqs(struct rzv2m_csi_priv *csi) in rzv2m_csi_disable_all_irqs() argument
251 rzv2m_csi_disable_irqs(csi, CSI_CNT_R_TRGR_E | CSI_CNT_T_TRGR_E | in rzv2m_csi_disable_all_irqs()
256 static inline void rzv2m_csi_clear_irqs(struct rzv2m_csi_priv *csi, u32 irqs) in rzv2m_csi_clear_irqs() argument
258 writel(irqs, csi->base + CSI_INT); in rzv2m_csi_clear_irqs()
261 static void rzv2m_csi_clear_all_irqs(struct rzv2m_csi_priv *csi) in rzv2m_csi_clear_all_irqs() argument
263 rzv2m_csi_clear_irqs(csi, CSI_INT_UNDER | CSI_INT_OVERF | in rzv2m_csi_clear_all_irqs()
268 static void rzv2m_csi_enable_irqs(struct rzv2m_csi_priv *csi, u32 enable_bits) in rzv2m_csi_enable_irqs() argument
270 u32 cnt = readl(csi->base + CSI_CNT); in rzv2m_csi_enable_irqs()
272 writel(cnt | enable_bits, csi->base + CSI_CNT); in rzv2m_csi_enable_irqs()
275 static int rzv2m_csi_wait_for_interrupt(struct rzv2m_csi_priv *csi, in rzv2m_csi_wait_for_interrupt() argument
280 rzv2m_csi_enable_irqs(csi, enable_bits); in rzv2m_csi_wait_for_interrupt()
282 ret = wait_event_timeout(csi->wait, in rzv2m_csi_wait_for_interrupt()
283 ((csi->status & wait_mask) == wait_mask) || in rzv2m_csi_wait_for_interrupt()
284 csi->errors, HZ); in rzv2m_csi_wait_for_interrupt()
286 rzv2m_csi_disable_irqs(csi, enable_bits); in rzv2m_csi_wait_for_interrupt()
288 if (csi->errors) in rzv2m_csi_wait_for_interrupt()
289 return -EIO; in rzv2m_csi_wait_for_interrupt()
292 return -ETIMEDOUT; in rzv2m_csi_wait_for_interrupt()
297 static int rzv2m_csi_wait_for_tx_empty(struct rzv2m_csi_priv *csi) in rzv2m_csi_wait_for_tx_empty() argument
301 if (readl(csi->base + CSI_OFIFOL) == 0) in rzv2m_csi_wait_for_tx_empty()
304 ret = rzv2m_csi_wait_for_interrupt(csi, CSI_INT_TREND, CSI_CNT_TREND_E); in rzv2m_csi_wait_for_tx_empty()
305 if (ret == -ETIMEDOUT) in rzv2m_csi_wait_for_tx_empty()
306 csi->errors |= TX_TIMEOUT_ERROR; in rzv2m_csi_wait_for_tx_empty()
311 static inline int rzv2m_csi_wait_for_rx_ready(struct rzv2m_csi_priv *csi) in rzv2m_csi_wait_for_rx_ready() argument
315 if (readl(csi->base + CSI_IFIFOL) == csi->bytes_to_transfer) in rzv2m_csi_wait_for_rx_ready()
318 ret = rzv2m_csi_wait_for_interrupt(csi, CSI_INT_R_TRGR, in rzv2m_csi_wait_for_rx_ready()
320 if (ret == -ETIMEDOUT) in rzv2m_csi_wait_for_rx_ready()
321 csi->errors |= RX_TIMEOUT_ERROR; in rzv2m_csi_wait_for_rx_ready()
328 struct rzv2m_csi_priv *csi = data; in rzv2m_csi_irq_handler() local
330 csi->status = readl(csi->base + CSI_INT); in rzv2m_csi_irq_handler()
331 rzv2m_csi_disable_irqs(csi, csi->status); in rzv2m_csi_irq_handler()
333 if (csi->status & CSI_INT_OVERF) in rzv2m_csi_irq_handler()
334 csi->errors |= OVERFLOW_ERROR; in rzv2m_csi_irq_handler()
335 if (csi->status & CSI_INT_UNDER) in rzv2m_csi_irq_handler()
336 csi->errors |= UNDERRUN_ERROR; in rzv2m_csi_irq_handler()
338 wake_up(&csi->wait); in rzv2m_csi_irq_handler()
343 static void rzv2m_csi_setup_clock(struct rzv2m_csi_priv *csi, u32 spi_hz) in rzv2m_csi_setup_clock() argument
345 unsigned long csiclk_rate = clk_get_rate(csi->csiclk); in rzv2m_csi_setup_clock()
346 unsigned long pclk_rate = clk_get_rate(csi->pclk); in rzv2m_csi_setup_clock()
352 * PCLK / 2. in rzv2m_csi_setup_clock()
355 clk_set_rate(csi->csiclk, csiclk_rate >> 1); in rzv2m_csi_setup_clock()
356 csiclk_rate = clk_get_rate(csi->csiclk); in rzv2m_csi_setup_clock()
358 clk_set_rate(csi->csiclk, csiclk_rate << 1); in rzv2m_csi_setup_clock()
359 csiclk_rate = clk_get_rate(csi->csiclk); in rzv2m_csi_setup_clock()
368 dev_dbg(csi->dev, "SPI clk rate is %ldHz\n", csiclk_rate / (cks << 1)); in rzv2m_csi_setup_clock()
370 rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_CKS, cks); in rzv2m_csi_setup_clock()
373 static void rzv2m_csi_setup_operating_mode(struct rzv2m_csi_priv *csi, in rzv2m_csi_setup_operating_mode() argument
376 if (t->rx_buf && !t->tx_buf) in rzv2m_csi_setup_operating_mode()
377 /* Reception-only mode */ in rzv2m_csi_setup_operating_mode()
378 rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_TRMD, 0); in rzv2m_csi_setup_operating_mode()
381 rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_TRMD, 1); in rzv2m_csi_setup_operating_mode()
383 csi->bytes_per_word = t->bits_per_word / 8; in rzv2m_csi_setup_operating_mode()
384 rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_CCL, in rzv2m_csi_setup_operating_mode()
385 csi->bytes_per_word == 2); in rzv2m_csi_setup_operating_mode()
390 struct rzv2m_csi_priv *csi = spi_controller_get_devdata(spi->controller); in rzv2m_csi_setup() local
393 rzv2m_csi_sw_reset(csi, 0); in rzv2m_csi_setup()
395 writel(CSI_MODE_SETUP, csi->base + CSI_MODE); in rzv2m_csi_setup()
398 rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_MODE, in rzv2m_csi_setup()
399 ~spi->mode & SPI_MODE_X_MASK); in rzv2m_csi_setup()
402 rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_DIR, in rzv2m_csi_setup()
403 !!(spi->mode & SPI_LSB_FIRST)); in rzv2m_csi_setup()
406 rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_SLAVE, 0); in rzv2m_csi_setup()
409 ret = rzv2m_csi_sw_reset(csi, 1); in rzv2m_csi_setup()
412 rzv2m_csi_sw_reset(csi, 0); in rzv2m_csi_setup()
418 rzv2m_csi_start_stop_operation(csi, 1, false); in rzv2m_csi_setup()
420 rzv2m_csi_start_stop_operation(csi, 0, false); in rzv2m_csi_setup()
425 static int rzv2m_csi_pio_transfer(struct rzv2m_csi_priv *csi) in rzv2m_csi_pio_transfer() argument
427 bool tx_completed = !csi->txbuf; in rzv2m_csi_pio_transfer()
428 bool rx_completed = !csi->rxbuf; in rzv2m_csi_pio_transfer()
432 writel(0, csi->base + CSI_OFIFOL); in rzv2m_csi_pio_transfer()
434 csi->bytes_sent = 0; in rzv2m_csi_pio_transfer()
435 csi->bytes_received = 0; in rzv2m_csi_pio_transfer()
436 csi->errors = 0; in rzv2m_csi_pio_transfer()
438 rzv2m_csi_disable_all_irqs(csi); in rzv2m_csi_pio_transfer()
439 rzv2m_csi_clear_all_irqs(csi); in rzv2m_csi_pio_transfer()
440 rzv2m_csi_enable_rx_trigger(csi, true); in rzv2m_csi_pio_transfer()
450 rzv2m_csi_calc_current_transfer(csi); in rzv2m_csi_pio_transfer()
451 rzv2m_csi_set_rx_fifo_trigger_level(csi); in rzv2m_csi_pio_transfer()
453 rzv2m_csi_enable_irqs(csi, CSI_INT_OVERF | CSI_INT_UNDER); in rzv2m_csi_pio_transfer()
456 writel(0, csi->base + CSI_IFIFOL); in rzv2m_csi_pio_transfer()
458 writel(readl(csi->base + CSI_INT), csi->base + CSI_INT); in rzv2m_csi_pio_transfer()
459 csi->status = 0; in rzv2m_csi_pio_transfer()
461 rzv2m_csi_start_stop_operation(csi, 1, false); in rzv2m_csi_pio_transfer()
464 if (csi->txbuf) { in rzv2m_csi_pio_transfer()
465 ret = rzv2m_csi_fill_txfifo(csi); in rzv2m_csi_pio_transfer()
469 ret = rzv2m_csi_wait_for_tx_empty(csi); in rzv2m_csi_pio_transfer()
473 if (csi->bytes_sent == csi->buffer_len) in rzv2m_csi_pio_transfer()
480 * csi->rxbuf. in rzv2m_csi_pio_transfer()
482 ret = rzv2m_csi_wait_for_rx_ready(csi); in rzv2m_csi_pio_transfer()
487 if (csi->rxbuf) { in rzv2m_csi_pio_transfer()
488 rzv2m_csi_start_stop_operation(csi, 0, false); in rzv2m_csi_pio_transfer()
490 ret = rzv2m_csi_read_rxfifo(csi); in rzv2m_csi_pio_transfer()
494 if (csi->bytes_received == csi->buffer_len) in rzv2m_csi_pio_transfer()
498 ret = rzv2m_csi_start_stop_operation(csi, 0, true); in rzv2m_csi_pio_transfer()
502 if (csi->errors) { in rzv2m_csi_pio_transfer()
503 ret = -EIO; in rzv2m_csi_pio_transfer()
508 rzv2m_csi_start_stop_operation(csi, 0, true); in rzv2m_csi_pio_transfer()
511 rzv2m_csi_disable_all_irqs(csi); in rzv2m_csi_pio_transfer()
512 rzv2m_csi_enable_rx_trigger(csi, false); in rzv2m_csi_pio_transfer()
513 rzv2m_csi_clear_all_irqs(csi); in rzv2m_csi_pio_transfer()
522 struct rzv2m_csi_priv *csi = spi_controller_get_devdata(controller); in rzv2m_csi_transfer_one() local
523 struct device *dev = csi->dev; in rzv2m_csi_transfer_one()
526 csi->txbuf = transfer->tx_buf; in rzv2m_csi_transfer_one()
527 csi->rxbuf = transfer->rx_buf; in rzv2m_csi_transfer_one()
528 csi->buffer_len = transfer->len; in rzv2m_csi_transfer_one()
530 rzv2m_csi_setup_operating_mode(csi, transfer); in rzv2m_csi_transfer_one()
532 rzv2m_csi_setup_clock(csi, transfer->speed_hz); in rzv2m_csi_transfer_one()
534 ret = rzv2m_csi_pio_transfer(csi); in rzv2m_csi_transfer_one()
536 if (csi->errors & UNDERRUN_ERROR) in rzv2m_csi_transfer_one()
538 if (csi->errors & OVERFLOW_ERROR) in rzv2m_csi_transfer_one()
540 if (csi->errors & TX_TIMEOUT_ERROR) in rzv2m_csi_transfer_one()
542 if (csi->errors & RX_TIMEOUT_ERROR) in rzv2m_csi_transfer_one()
552 struct device *dev = &pdev->dev; in rzv2m_csi_probe()
553 struct rzv2m_csi_priv *csi; in rzv2m_csi_probe() local
558 controller = devm_spi_alloc_host(dev, sizeof(*csi)); in rzv2m_csi_probe()
560 return -ENOMEM; in rzv2m_csi_probe()
562 csi = spi_controller_get_devdata(controller); in rzv2m_csi_probe()
563 platform_set_drvdata(pdev, csi); in rzv2m_csi_probe()
565 csi->dev = dev; in rzv2m_csi_probe()
566 csi->controller = controller; in rzv2m_csi_probe()
568 csi->base = devm_platform_ioremap_resource(pdev, 0); in rzv2m_csi_probe()
569 if (IS_ERR(csi->base)) in rzv2m_csi_probe()
570 return PTR_ERR(csi->base); in rzv2m_csi_probe()
576 csi->csiclk = devm_clk_get(dev, "csiclk"); in rzv2m_csi_probe()
577 if (IS_ERR(csi->csiclk)) in rzv2m_csi_probe()
578 return dev_err_probe(dev, PTR_ERR(csi->csiclk), in rzv2m_csi_probe()
581 csi->pclk = devm_clk_get(dev, "pclk"); in rzv2m_csi_probe()
582 if (IS_ERR(csi->pclk)) in rzv2m_csi_probe()
583 return dev_err_probe(dev, PTR_ERR(csi->pclk), in rzv2m_csi_probe()
584 "could not get pclk\n"); in rzv2m_csi_probe()
590 init_waitqueue_head(&csi->wait); in rzv2m_csi_probe()
592 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; in rzv2m_csi_probe()
593 controller->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8); in rzv2m_csi_probe()
594 controller->setup = rzv2m_csi_setup; in rzv2m_csi_probe()
595 controller->transfer_one = rzv2m_csi_transfer_one; in rzv2m_csi_probe()
596 controller->use_gpio_descriptors = true; in rzv2m_csi_probe()
598 device_set_node(&controller->dev, dev_fwnode(dev)); in rzv2m_csi_probe()
601 dev_name(dev), csi); in rzv2m_csi_probe()
613 ret = rzv2m_csi_sw_reset(csi, 1); in rzv2m_csi_probe()
617 ret = clk_prepare_enable(csi->csiclk); in rzv2m_csi_probe()
623 clk_disable_unprepare(csi->csiclk); in rzv2m_csi_probe()
632 struct rzv2m_csi_priv *csi = platform_get_drvdata(pdev); in rzv2m_csi_remove() local
634 spi_unregister_controller(csi->controller); in rzv2m_csi_remove()
635 rzv2m_csi_sw_reset(csi, 1); in rzv2m_csi_remove()
636 clk_disable_unprepare(csi->csiclk); in rzv2m_csi_remove()
640 { .compatible = "renesas,rzv2m-csi" },