Lines Matching +full:qup +full:- +full:config
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
18 #include <linux/dma-mapping.h>
115 #define SPI_MAX_XFER (SZ_64K - 64)
157 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_is_flag_set()
173 return controller->n_words * controller->w_size; in spi_qup_len()
178 u32 opstate = readl_relaxed(controller->base + QUP_STATE); in spi_qup_is_valid_state()
194 return -EIO; in spi_qup_set_state()
198 dev_dbg(controller->dev, "invalid state for %ld,us %d\n", in spi_qup_set_state()
201 cur_state = readl_relaxed(controller->base + QUP_STATE); in spi_qup_set_state()
208 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
209 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
213 writel_relaxed(cur_state, controller->base + QUP_STATE); in spi_qup_set_state()
222 return -EIO; in spi_qup_set_state()
230 u8 *rx_buf = controller->rx_buf; in spi_qup_read_from_fifo()
234 for (; num_words; num_words--) { in spi_qup_read_from_fifo()
236 word = readl_relaxed(controller->base + QUP_INPUT_FIFO); in spi_qup_read_from_fifo()
238 num_bytes = min_t(int, spi_qup_len(controller) - in spi_qup_read_from_fifo()
239 controller->rx_bytes, in spi_qup_read_from_fifo()
240 controller->w_size); in spi_qup_read_from_fifo()
243 controller->rx_bytes += num_bytes; in spi_qup_read_from_fifo()
247 for (i = 0; i < num_bytes; i++, controller->rx_bytes++) { in spi_qup_read_from_fifo()
255 shift *= (controller->w_size - i - 1); in spi_qup_read_from_fifo()
256 rx_buf[controller->rx_bytes] = word >> shift; in spi_qup_read_from_fifo()
264 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; in spi_qup_read()
266 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes, in spi_qup_read()
267 controller->w_size); in spi_qup_read()
268 words_per_block = controller->in_blk_sz >> 2; in spi_qup_read()
273 controller->base + QUP_OPERATIONAL); in spi_qup_read()
292 remainder -= num_words; in spi_qup_read()
309 *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_read()
312 controller->base + QUP_OPERATIONAL); in spi_qup_read()
318 const u8 *tx_buf = controller->tx_buf; in spi_qup_write_to_fifo()
322 for (; num_words; num_words--) { in spi_qup_write_to_fifo()
325 num_bytes = min_t(int, spi_qup_len(controller) - in spi_qup_write_to_fifo()
326 controller->tx_bytes, in spi_qup_write_to_fifo()
327 controller->w_size); in spi_qup_write_to_fifo()
330 data = tx_buf[controller->tx_bytes + i]; in spi_qup_write_to_fifo()
331 word |= data << (BITS_PER_BYTE * (3 - i)); in spi_qup_write_to_fifo()
334 controller->tx_bytes += num_bytes; in spi_qup_write_to_fifo()
336 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); in spi_qup_write_to_fifo()
342 struct spi_qup *qup = data; in spi_qup_dma_done() local
344 complete(&qup->done); in spi_qup_dma_done()
349 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; in spi_qup_write()
352 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes, in spi_qup_write()
353 controller->w_size); in spi_qup_write()
354 words_per_block = controller->out_blk_sz >> 2; in spi_qup_write()
359 controller->base + QUP_OPERATIONAL); in spi_qup_write()
378 remainder -= num_words; in spi_qup_write()
392 struct spi_qup *qup = spi_controller_get_devdata(host); in spi_qup_prep_sg() local
399 chan = host->dma_tx; in spi_qup_prep_sg()
401 chan = host->dma_rx; in spi_qup_prep_sg()
405 return desc ? PTR_ERR(desc) : -EINVAL; in spi_qup_prep_sg()
407 desc->callback = callback; in spi_qup_prep_sg()
408 desc->callback_param = qup; in spi_qup_prep_sg()
418 if (xfer->tx_buf) in spi_qup_dma_terminate()
419 dmaengine_terminate_all(host->dma_tx); in spi_qup_dma_terminate()
420 if (xfer->rx_buf) in spi_qup_dma_terminate()
421 dmaengine_terminate_all(host->dma_rx); in spi_qup_dma_terminate()
448 struct spi_controller *host = spi->controller; in spi_qup_do_dma()
449 struct spi_qup *qup = spi_controller_get_devdata(host); in spi_qup_do_dma() local
453 if (xfer->rx_buf) in spi_qup_do_dma()
455 else if (xfer->tx_buf) in spi_qup_do_dma()
458 rx_sgl = xfer->rx_sg.sgl; in spi_qup_do_dma()
459 tx_sgl = xfer->tx_sg.sgl; in spi_qup_do_dma()
465 qup->n_words = spi_qup_sgl_get_nents_len(rx_sgl, in spi_qup_do_dma()
466 SPI_MAX_XFER, &rx_nents) / qup->w_size; in spi_qup_do_dma()
468 qup->n_words = spi_qup_sgl_get_nents_len(tx_sgl, in spi_qup_do_dma()
469 SPI_MAX_XFER, &tx_nents) / qup->w_size; in spi_qup_do_dma()
470 if (!qup->n_words) in spi_qup_do_dma()
471 return -EIO; in spi_qup_do_dma()
477 /* before issuing the descriptors, set the QUP to run */ in spi_qup_do_dma()
478 ret = spi_qup_set_state(qup, QUP_STATE_RUN); in spi_qup_do_dma()
480 dev_warn(qup->dev, "cannot set RUN state\n"); in spi_qup_do_dma()
488 dma_async_issue_pending(host->dma_rx); in spi_qup_do_dma()
497 dma_async_issue_pending(host->dma_tx); in spi_qup_do_dma()
500 if (!wait_for_completion_timeout(&qup->done, timeout)) in spi_qup_do_dma()
501 return -ETIMEDOUT; in spi_qup_do_dma()
503 for (; rx_sgl && rx_nents--; rx_sgl = sg_next(rx_sgl)) in spi_qup_do_dma()
505 for (; tx_sgl && tx_nents--; tx_sgl = sg_next(tx_sgl)) in spi_qup_do_dma()
516 struct spi_controller *host = spi->controller; in spi_qup_do_pio()
517 struct spi_qup *qup = spi_controller_get_devdata(host); in spi_qup_do_pio() local
520 n_words = qup->n_words; in spi_qup_do_pio()
522 qup->rx_buf = xfer->rx_buf; in spi_qup_do_pio()
523 qup->tx_buf = xfer->tx_buf; in spi_qup_do_pio()
527 qup->n_words = SPI_MAX_XFER; in spi_qup_do_pio()
529 qup->n_words = n_words % SPI_MAX_XFER; in spi_qup_do_pio()
531 if (qup->tx_buf && offset) in spi_qup_do_pio()
532 qup->tx_buf = xfer->tx_buf + offset * SPI_MAX_XFER; in spi_qup_do_pio()
534 if (qup->rx_buf && offset) in spi_qup_do_pio()
535 qup->rx_buf = xfer->rx_buf + offset * SPI_MAX_XFER; in spi_qup_do_pio()
541 if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32))) in spi_qup_do_pio()
542 qup->mode = QUP_IO_M_MODE_FIFO; in spi_qup_do_pio()
548 ret = spi_qup_set_state(qup, QUP_STATE_RUN); in spi_qup_do_pio()
550 dev_warn(qup->dev, "cannot set RUN state\n"); in spi_qup_do_pio()
554 ret = spi_qup_set_state(qup, QUP_STATE_PAUSE); in spi_qup_do_pio()
556 dev_warn(qup->dev, "cannot set PAUSE state\n"); in spi_qup_do_pio()
560 if (qup->mode == QUP_IO_M_MODE_FIFO) in spi_qup_do_pio()
561 spi_qup_write(qup); in spi_qup_do_pio()
563 ret = spi_qup_set_state(qup, QUP_STATE_RUN); in spi_qup_do_pio()
565 dev_warn(qup->dev, "cannot set RUN state\n"); in spi_qup_do_pio()
569 if (!wait_for_completion_timeout(&qup->done, timeout)) in spi_qup_do_pio()
570 return -ETIMEDOUT; in spi_qup_do_pio()
573 } while (iterations--); in spi_qup_do_pio()
582 remainder_tx = DIV_ROUND_UP(spi_qup_len(controller) - in spi_qup_data_pending()
583 controller->tx_bytes, controller->w_size); in spi_qup_data_pending()
585 remainder_rx = DIV_ROUND_UP(spi_qup_len(controller) - in spi_qup_data_pending()
586 controller->rx_bytes, controller->w_size); in spi_qup_data_pending()
597 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
598 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
599 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
601 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
602 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
606 dev_warn(controller->dev, "OUTPUT_OVER_RUN\n"); in spi_qup_qup_irq()
608 dev_warn(controller->dev, "INPUT_UNDER_RUN\n"); in spi_qup_qup_irq()
610 dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n"); in spi_qup_qup_irq()
612 dev_warn(controller->dev, "INPUT_OVER_RUN\n"); in spi_qup_qup_irq()
614 error = -EIO; in spi_qup_qup_irq()
619 dev_warn(controller->dev, "CLK_OVER_RUN\n"); in spi_qup_qup_irq()
621 dev_warn(controller->dev, "CLK_UNDER_RUN\n"); in spi_qup_qup_irq()
623 error = -EIO; in spi_qup_qup_irq()
626 spin_lock(&controller->lock); in spi_qup_qup_irq()
627 if (!controller->error) in spi_qup_qup_irq()
628 controller->error = error; in spi_qup_qup_irq()
629 spin_unlock(&controller->lock); in spi_qup_qup_irq()
631 if (spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_qup_irq()
632 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
641 complete(&controller->done); in spi_qup_qup_irq()
645 complete(&controller->done); in spi_qup_qup_irq()
648 if (!spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_qup_irq()
652 complete(&controller->done); in spi_qup_qup_irq()
661 struct spi_qup *controller = spi_controller_get_devdata(spi->controller); in spi_qup_io_prep()
664 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { in spi_qup_io_prep()
665 dev_err(controller->dev, "too big size for loopback %d > %d\n", in spi_qup_io_prep()
666 xfer->len, controller->in_fifo_sz); in spi_qup_io_prep()
667 return -EIO; in spi_qup_io_prep()
670 ret = clk_set_rate(controller->cclk, xfer->speed_hz); in spi_qup_io_prep()
672 dev_err(controller->dev, "fail to set frequency %d", in spi_qup_io_prep()
673 xfer->speed_hz); in spi_qup_io_prep()
674 return -EIO; in spi_qup_io_prep()
677 controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8); in spi_qup_io_prep()
678 controller->n_words = xfer->len / controller->w_size; in spi_qup_io_prep()
680 if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32))) in spi_qup_io_prep()
681 controller->mode = QUP_IO_M_MODE_FIFO; in spi_qup_io_prep()
682 else if (spi->controller->can_dma && in spi_qup_io_prep()
683 spi->controller->can_dma(spi->controller, spi, xfer) && in spi_qup_io_prep()
684 spi->controller->cur_msg_mapped) in spi_qup_io_prep()
685 controller->mode = QUP_IO_M_MODE_BAM; in spi_qup_io_prep()
687 controller->mode = QUP_IO_M_MODE_BLOCK; in spi_qup_io_prep()
692 /* prep qup for another spi transaction of specific type */
695 struct spi_qup *controller = spi_controller_get_devdata(spi->controller); in spi_qup_io_config()
696 u32 config, iomode, control; in spi_qup_io_config() local
699 spin_lock_irqsave(&controller->lock, flags); in spi_qup_io_config()
700 controller->xfer = xfer; in spi_qup_io_config()
701 controller->error = 0; in spi_qup_io_config()
702 controller->rx_bytes = 0; in spi_qup_io_config()
703 controller->tx_bytes = 0; in spi_qup_io_config()
704 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_io_config()
708 dev_err(controller->dev, "cannot set RESET state\n"); in spi_qup_io_config()
709 return -EIO; in spi_qup_io_config()
712 switch (controller->mode) { in spi_qup_io_config()
714 writel_relaxed(controller->n_words, in spi_qup_io_config()
715 controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
716 writel_relaxed(controller->n_words, in spi_qup_io_config()
717 controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
719 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
720 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
723 writel_relaxed(controller->n_words, in spi_qup_io_config()
724 controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
725 writel_relaxed(controller->n_words, in spi_qup_io_config()
726 controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
728 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
729 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
731 if (!controller->qup_v1) { in spi_qup_io_config()
734 input_cnt = controller->base + QUP_MX_INPUT_CNT; in spi_qup_io_config()
738 * That case is a non-balanced transfer when there is in spi_qup_io_config()
741 if (xfer->tx_buf) in spi_qup_io_config()
744 writel_relaxed(controller->n_words, input_cnt); in spi_qup_io_config()
746 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
750 reinit_completion(&controller->done); in spi_qup_io_config()
751 writel_relaxed(controller->n_words, in spi_qup_io_config()
752 controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
753 writel_relaxed(controller->n_words, in spi_qup_io_config()
754 controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
756 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
757 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
760 dev_err(controller->dev, "unknown mode = %d\n", in spi_qup_io_config()
761 controller->mode); in spi_qup_io_config()
762 return -EIO; in spi_qup_io_config()
765 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); in spi_qup_io_config()
769 if (!spi_qup_is_dma_xfer(controller->mode)) in spi_qup_io_config()
774 iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); in spi_qup_io_config()
775 iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); in spi_qup_io_config()
777 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES); in spi_qup_io_config()
779 control = readl_relaxed(controller->base + SPI_IO_CONTROL); in spi_qup_io_config()
781 if (spi->mode & SPI_CPOL) in spi_qup_io_config()
786 writel_relaxed(control, controller->base + SPI_IO_CONTROL); in spi_qup_io_config()
788 config = readl_relaxed(controller->base + SPI_CONFIG); in spi_qup_io_config()
790 if (spi->mode & SPI_LOOP) in spi_qup_io_config()
791 config |= SPI_CONFIG_LOOPBACK; in spi_qup_io_config()
793 config &= ~SPI_CONFIG_LOOPBACK; in spi_qup_io_config()
795 if (spi->mode & SPI_CPHA) in spi_qup_io_config()
796 config &= ~SPI_CONFIG_INPUT_FIRST; in spi_qup_io_config()
798 config |= SPI_CONFIG_INPUT_FIRST; in spi_qup_io_config()
801 * HS_MODE improves signal stability for spi-clk high rates, in spi_qup_io_config()
804 if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP)) in spi_qup_io_config()
805 config |= SPI_CONFIG_HS_MODE; in spi_qup_io_config()
807 config &= ~SPI_CONFIG_HS_MODE; in spi_qup_io_config()
809 writel_relaxed(config, controller->base + SPI_CONFIG); in spi_qup_io_config()
811 config = readl_relaxed(controller->base + QUP_CONFIG); in spi_qup_io_config()
812 config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N); in spi_qup_io_config()
813 config |= xfer->bits_per_word - 1; in spi_qup_io_config()
814 config |= QUP_CONFIG_SPI_MODE; in spi_qup_io_config()
816 if (spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_io_config()
817 if (!xfer->tx_buf) in spi_qup_io_config()
818 config |= QUP_CONFIG_NO_OUTPUT; in spi_qup_io_config()
819 if (!xfer->rx_buf) in spi_qup_io_config()
820 config |= QUP_CONFIG_NO_INPUT; in spi_qup_io_config()
823 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_io_config()
826 if (!controller->qup_v1) { in spi_qup_io_config()
834 if (spi_qup_is_dma_xfer(controller->mode)) in spi_qup_io_config()
837 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK); in spi_qup_io_config()
855 timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC); in spi_qup_transfer_one()
857 xfer->len) * 8, timeout); in spi_qup_transfer_one()
860 reinit_completion(&controller->done); in spi_qup_transfer_one()
862 spin_lock_irqsave(&controller->lock, flags); in spi_qup_transfer_one()
863 controller->xfer = xfer; in spi_qup_transfer_one()
864 controller->error = 0; in spi_qup_transfer_one()
865 controller->rx_bytes = 0; in spi_qup_transfer_one()
866 controller->tx_bytes = 0; in spi_qup_transfer_one()
867 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_transfer_one()
869 if (spi_qup_is_dma_xfer(controller->mode)) in spi_qup_transfer_one()
875 spin_lock_irqsave(&controller->lock, flags); in spi_qup_transfer_one()
877 ret = controller->error; in spi_qup_transfer_one()
878 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_transfer_one()
880 if (ret && spi_qup_is_dma_xfer(controller->mode)) in spi_qup_transfer_one()
889 struct spi_qup *qup = spi_controller_get_devdata(host); in spi_qup_can_dma() local
893 if (xfer->rx_buf) { in spi_qup_can_dma()
894 if (!IS_ALIGNED((size_t)xfer->rx_buf, dma_align) || in spi_qup_can_dma()
895 IS_ERR_OR_NULL(host->dma_rx)) in spi_qup_can_dma()
897 if (qup->qup_v1 && (xfer->len % qup->in_blk_sz)) in spi_qup_can_dma()
901 if (xfer->tx_buf) { in spi_qup_can_dma()
902 if (!IS_ALIGNED((size_t)xfer->tx_buf, dma_align) || in spi_qup_can_dma()
903 IS_ERR_OR_NULL(host->dma_tx)) in spi_qup_can_dma()
905 if (qup->qup_v1 && (xfer->len % qup->out_blk_sz)) in spi_qup_can_dma()
909 n_words = xfer->len / DIV_ROUND_UP(xfer->bits_per_word, 8); in spi_qup_can_dma()
910 if (n_words <= (qup->in_fifo_sz / sizeof(u32))) in spi_qup_can_dma()
918 if (!IS_ERR_OR_NULL(host->dma_rx)) in spi_qup_release_dma()
919 dma_release_channel(host->dma_rx); in spi_qup_release_dma()
920 if (!IS_ERR_OR_NULL(host->dma_tx)) in spi_qup_release_dma()
921 dma_release_channel(host->dma_tx); in spi_qup_release_dma()
927 struct dma_slave_config *rx_conf = &spi->rx_conf, in spi_qup_init_dma()
928 *tx_conf = &spi->tx_conf; in spi_qup_init_dma()
929 struct device *dev = spi->dev; in spi_qup_init_dma()
933 host->dma_rx = dma_request_chan(dev, "rx"); in spi_qup_init_dma()
934 if (IS_ERR(host->dma_rx)) in spi_qup_init_dma()
935 return PTR_ERR(host->dma_rx); in spi_qup_init_dma()
937 host->dma_tx = dma_request_chan(dev, "tx"); in spi_qup_init_dma()
938 if (IS_ERR(host->dma_tx)) { in spi_qup_init_dma()
939 ret = PTR_ERR(host->dma_tx); in spi_qup_init_dma()
944 rx_conf->direction = DMA_DEV_TO_MEM; in spi_qup_init_dma()
945 rx_conf->device_fc = 1; in spi_qup_init_dma()
946 rx_conf->src_addr = base + QUP_INPUT_FIFO; in spi_qup_init_dma()
947 rx_conf->src_maxburst = spi->in_blk_sz; in spi_qup_init_dma()
949 tx_conf->direction = DMA_MEM_TO_DEV; in spi_qup_init_dma()
950 tx_conf->device_fc = 1; in spi_qup_init_dma()
951 tx_conf->dst_addr = base + QUP_OUTPUT_FIFO; in spi_qup_init_dma()
952 tx_conf->dst_maxburst = spi->out_blk_sz; in spi_qup_init_dma()
954 ret = dmaengine_slave_config(host->dma_rx, rx_conf); in spi_qup_init_dma()
960 ret = dmaengine_slave_config(host->dma_tx, tx_conf); in spi_qup_init_dma()
969 dma_release_channel(host->dma_tx); in spi_qup_init_dma()
971 dma_release_channel(host->dma_rx); in spi_qup_init_dma()
981 controller = spi_controller_get_devdata(spi->controller); in spi_qup_set_cs()
982 spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL); in spi_qup_set_cs()
990 writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL); in spi_qup_set_cs()
1004 dev = &pdev->dev; in spi_qup_probe()
1022 if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq)) in spi_qup_probe()
1027 return -ENXIO; in spi_qup_probe()
1033 return -ENOMEM; in spi_qup_probe()
1036 /* use num-cs unless not present or out of range */ in spi_qup_probe()
1037 if (of_property_read_u32(dev->of_node, "num-cs", &num_cs) || in spi_qup_probe()
1039 host->num_chipselect = SPI_NUM_CHIPSELECTS; in spi_qup_probe()
1041 host->num_chipselect = num_cs; in spi_qup_probe()
1043 host->use_gpio_descriptors = true; in spi_qup_probe()
1044 host->max_native_cs = SPI_NUM_CHIPSELECTS; in spi_qup_probe()
1045 host->bus_num = pdev->id; in spi_qup_probe()
1046 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; in spi_qup_probe()
1047 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in spi_qup_probe()
1048 host->max_speed_hz = max_freq; in spi_qup_probe()
1049 host->transfer_one = spi_qup_transfer_one; in spi_qup_probe()
1050 host->dev.of_node = pdev->dev.of_node; in spi_qup_probe()
1051 host->auto_runtime_pm = true; in spi_qup_probe()
1052 host->dma_alignment = dma_get_cache_alignment(); in spi_qup_probe()
1053 host->max_dma_len = SPI_MAX_XFER; in spi_qup_probe()
1059 controller->dev = dev; in spi_qup_probe()
1060 controller->base = base; in spi_qup_probe()
1061 controller->iclk = iclk; in spi_qup_probe()
1062 controller->cclk = cclk; in spi_qup_probe()
1063 controller->irq = irq; in spi_qup_probe()
1065 ret = spi_qup_init_dma(host, res->start); in spi_qup_probe()
1066 if (ret == -EPROBE_DEFER) in spi_qup_probe()
1069 host->can_dma = spi_qup_can_dma; in spi_qup_probe()
1071 controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev); in spi_qup_probe()
1073 if (!controller->qup_v1) in spi_qup_probe()
1074 host->set_cs = spi_qup_set_cs; in spi_qup_probe()
1076 spin_lock_init(&controller->lock); in spi_qup_probe()
1077 init_completion(&controller->done); in spi_qup_probe()
1096 controller->out_blk_sz = size * 16; in spi_qup_probe()
1098 controller->out_blk_sz = 4; in spi_qup_probe()
1102 controller->in_blk_sz = size * 16; in spi_qup_probe()
1104 controller->in_blk_sz = 4; in spi_qup_probe()
1107 controller->out_fifo_sz = controller->out_blk_sz * (2 << size); in spi_qup_probe()
1110 controller->in_fifo_sz = controller->in_blk_sz * (2 << size); in spi_qup_probe()
1113 controller->in_blk_sz, controller->in_fifo_sz, in spi_qup_probe()
1114 controller->out_blk_sz, controller->out_fifo_sz); in spi_qup_probe()
1127 if (!controller->qup_v1) in spi_qup_probe()
1133 /* if earlier version of the QUP, disable INPUT_OVERRUN */ in spi_qup_probe()
1134 if (controller->qup_v1) in spi_qup_probe()
1143 IRQF_TRIGGER_HIGH, pdev->name, controller); in spi_qup_probe()
1159 pm_runtime_disable(&pdev->dev); in spi_qup_probe()
1175 u32 config; in spi_qup_pm_suspend_runtime() local
1178 config = readl(controller->base + QUP_CONFIG); in spi_qup_pm_suspend_runtime()
1179 config |= QUP_CONFIG_CLOCK_AUTO_GATE; in spi_qup_pm_suspend_runtime()
1180 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_pm_suspend_runtime()
1182 clk_disable_unprepare(controller->cclk); in spi_qup_pm_suspend_runtime()
1183 clk_disable_unprepare(controller->iclk); in spi_qup_pm_suspend_runtime()
1192 u32 config; in spi_qup_pm_resume_runtime() local
1195 ret = clk_prepare_enable(controller->iclk); in spi_qup_pm_resume_runtime()
1199 ret = clk_prepare_enable(controller->cclk); in spi_qup_pm_resume_runtime()
1201 clk_disable_unprepare(controller->iclk); in spi_qup_pm_resume_runtime()
1206 config = readl_relaxed(controller->base + QUP_CONFIG); in spi_qup_pm_resume_runtime()
1207 config &= ~QUP_CONFIG_CLOCK_AUTO_GATE; in spi_qup_pm_resume_runtime()
1208 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_pm_resume_runtime()
1233 clk_disable_unprepare(controller->cclk); in spi_qup_suspend()
1234 clk_disable_unprepare(controller->iclk); in spi_qup_suspend()
1244 ret = clk_prepare_enable(controller->iclk); in spi_qup_resume()
1248 ret = clk_prepare_enable(controller->cclk); in spi_qup_resume()
1250 clk_disable_unprepare(controller->iclk); in spi_qup_resume()
1265 clk_disable_unprepare(controller->cclk); in spi_qup_resume()
1266 clk_disable_unprepare(controller->iclk); in spi_qup_resume()
1273 struct spi_controller *host = dev_get_drvdata(&pdev->dev); in spi_qup_remove()
1277 ret = pm_runtime_get_sync(&pdev->dev); in spi_qup_remove()
1282 dev_warn(&pdev->dev, "failed to reset controller (%pe)\n", in spi_qup_remove()
1285 clk_disable_unprepare(controller->cclk); in spi_qup_remove()
1286 clk_disable_unprepare(controller->iclk); in spi_qup_remove()
1288 dev_warn(&pdev->dev, "failed to resume, skip hw disable (%pe)\n", in spi_qup_remove()
1294 pm_runtime_put_noidle(&pdev->dev); in spi_qup_remove()
1295 pm_runtime_disable(&pdev->dev); in spi_qup_remove()
1299 { .compatible = "qcom,spi-qup-v1.1.1", .data = (void *)1, },
1300 { .compatible = "qcom,spi-qup-v2.1.1", },
1301 { .compatible = "qcom,spi-qup-v2.2.1", },