Lines Matching full:controller
155 static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag) in spi_qup_is_flag_set() argument
157 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_is_flag_set()
171 static inline unsigned int spi_qup_len(struct spi_qup *controller) in spi_qup_len() argument
173 return controller->n_words * controller->w_size; in spi_qup_len()
176 static inline bool spi_qup_is_valid_state(struct spi_qup *controller) in spi_qup_is_valid_state() argument
178 u32 opstate = readl_relaxed(controller->base + QUP_STATE); in spi_qup_is_valid_state()
183 static int spi_qup_set_state(struct spi_qup *controller, u32 state) in spi_qup_set_state() argument
189 while (!spi_qup_is_valid_state(controller)) { in spi_qup_set_state()
198 dev_dbg(controller->dev, "invalid state for %ld,us %d\n", in spi_qup_set_state()
201 cur_state = readl_relaxed(controller->base + QUP_STATE); in spi_qup_set_state()
208 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
209 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
213 writel_relaxed(cur_state, controller->base + QUP_STATE); in spi_qup_set_state()
217 while (!spi_qup_is_valid_state(controller)) { in spi_qup_set_state()
228 static void spi_qup_read_from_fifo(struct spi_qup *controller, u32 num_words) in spi_qup_read_from_fifo() argument
230 u8 *rx_buf = controller->rx_buf; in spi_qup_read_from_fifo()
236 word = readl_relaxed(controller->base + QUP_INPUT_FIFO); in spi_qup_read_from_fifo()
238 num_bytes = min_t(int, spi_qup_len(controller) - in spi_qup_read_from_fifo()
239 controller->rx_bytes, in spi_qup_read_from_fifo()
240 controller->w_size); in spi_qup_read_from_fifo()
243 controller->rx_bytes += num_bytes; in spi_qup_read_from_fifo()
247 for (i = 0; i < num_bytes; i++, controller->rx_bytes++) { in spi_qup_read_from_fifo()
255 shift *= (controller->w_size - i - 1); in spi_qup_read_from_fifo()
256 rx_buf[controller->rx_bytes] = word >> shift; in spi_qup_read_from_fifo()
261 static void spi_qup_read(struct spi_qup *controller, u32 *opflags) in spi_qup_read() argument
264 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; in spi_qup_read()
266 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes, in spi_qup_read()
267 controller->w_size); in spi_qup_read()
268 words_per_block = controller->in_blk_sz >> 2; in spi_qup_read()
273 controller->base + QUP_OPERATIONAL); in spi_qup_read()
282 if (!spi_qup_is_flag_set(controller, in spi_qup_read()
290 spi_qup_read_from_fifo(controller, num_words); in spi_qup_read()
295 if (is_block_mode && !spi_qup_is_flag_set(controller, in spi_qup_read()
309 *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_read()
312 controller->base + QUP_OPERATIONAL); in spi_qup_read()
316 static void spi_qup_write_to_fifo(struct spi_qup *controller, u32 num_words) in spi_qup_write_to_fifo() argument
318 const u8 *tx_buf = controller->tx_buf; in spi_qup_write_to_fifo()
325 num_bytes = min_t(int, spi_qup_len(controller) - in spi_qup_write_to_fifo()
326 controller->tx_bytes, in spi_qup_write_to_fifo()
327 controller->w_size); in spi_qup_write_to_fifo()
330 data = tx_buf[controller->tx_bytes + i]; in spi_qup_write_to_fifo()
334 controller->tx_bytes += num_bytes; in spi_qup_write_to_fifo()
336 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); in spi_qup_write_to_fifo()
347 static void spi_qup_write(struct spi_qup *controller) in spi_qup_write() argument
349 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; in spi_qup_write()
352 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes, in spi_qup_write()
353 controller->w_size); in spi_qup_write()
354 words_per_block = controller->out_blk_sz >> 2; in spi_qup_write()
359 controller->base + QUP_OPERATIONAL); in spi_qup_write()
369 if (spi_qup_is_flag_set(controller, in spi_qup_write()
376 spi_qup_write_to_fifo(controller, num_words); in spi_qup_write()
381 if (is_block_mode && !spi_qup_is_flag_set(controller, in spi_qup_write()
448 struct spi_controller *host = spi->controller; in spi_qup_do_dma()
516 struct spi_controller *host = spi->controller; in spi_qup_do_pio()
578 static bool spi_qup_data_pending(struct spi_qup *controller) in spi_qup_data_pending() argument
582 remainder_tx = DIV_ROUND_UP(spi_qup_len(controller) - in spi_qup_data_pending()
583 controller->tx_bytes, controller->w_size); in spi_qup_data_pending()
585 remainder_rx = DIV_ROUND_UP(spi_qup_len(controller) - in spi_qup_data_pending()
586 controller->rx_bytes, controller->w_size); in spi_qup_data_pending()
593 struct spi_qup *controller = dev_id; in spi_qup_qup_irq() local
597 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
598 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
599 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
601 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
602 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
606 dev_warn(controller->dev, "OUTPUT_OVER_RUN\n"); in spi_qup_qup_irq()
608 dev_warn(controller->dev, "INPUT_UNDER_RUN\n"); in spi_qup_qup_irq()
610 dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n"); in spi_qup_qup_irq()
612 dev_warn(controller->dev, "INPUT_OVER_RUN\n"); in spi_qup_qup_irq()
619 dev_warn(controller->dev, "CLK_OVER_RUN\n"); in spi_qup_qup_irq()
621 dev_warn(controller->dev, "CLK_UNDER_RUN\n"); in spi_qup_qup_irq()
626 spin_lock(&controller->lock); in spi_qup_qup_irq()
627 if (!controller->error) in spi_qup_qup_irq()
628 controller->error = error; in spi_qup_qup_irq()
629 spin_unlock(&controller->lock); in spi_qup_qup_irq()
631 if (spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_qup_irq()
632 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
635 spi_qup_read(controller, &opflags); in spi_qup_qup_irq()
638 spi_qup_write(controller); in spi_qup_qup_irq()
640 if (!spi_qup_data_pending(controller)) in spi_qup_qup_irq()
641 complete(&controller->done); in spi_qup_qup_irq()
645 complete(&controller->done); in spi_qup_qup_irq()
648 if (!spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_qup_irq()
649 if (spi_qup_data_pending(controller)) in spi_qup_qup_irq()
652 complete(&controller->done); in spi_qup_qup_irq()
661 struct spi_qup *controller = spi_controller_get_devdata(spi->controller); in spi_qup_io_prep() local
664 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { in spi_qup_io_prep()
665 dev_err(controller->dev, "too big size for loopback %d > %d\n", in spi_qup_io_prep()
666 xfer->len, controller->in_fifo_sz); in spi_qup_io_prep()
670 ret = clk_set_rate(controller->cclk, xfer->speed_hz); in spi_qup_io_prep()
672 dev_err(controller->dev, "fail to set frequency %d", in spi_qup_io_prep()
677 controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8); in spi_qup_io_prep()
678 controller->n_words = xfer->len / controller->w_size; in spi_qup_io_prep()
680 if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32))) in spi_qup_io_prep()
681 controller->mode = QUP_IO_M_MODE_FIFO; in spi_qup_io_prep()
682 else if (spi->controller->can_dma && in spi_qup_io_prep()
683 spi->controller->can_dma(spi->controller, spi, xfer) && in spi_qup_io_prep()
684 spi->controller->cur_msg_mapped) in spi_qup_io_prep()
685 controller->mode = QUP_IO_M_MODE_BAM; in spi_qup_io_prep()
687 controller->mode = QUP_IO_M_MODE_BLOCK; in spi_qup_io_prep()
695 struct spi_qup *controller = spi_controller_get_devdata(spi->controller); in spi_qup_io_config() local
699 spin_lock_irqsave(&controller->lock, flags); in spi_qup_io_config()
700 controller->xfer = xfer; in spi_qup_io_config()
701 controller->error = 0; in spi_qup_io_config()
702 controller->rx_bytes = 0; in spi_qup_io_config()
703 controller->tx_bytes = 0; in spi_qup_io_config()
704 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_io_config()
707 if (spi_qup_set_state(controller, QUP_STATE_RESET)) { in spi_qup_io_config()
708 dev_err(controller->dev, "cannot set RESET state\n"); in spi_qup_io_config()
712 switch (controller->mode) { in spi_qup_io_config()
714 writel_relaxed(controller->n_words, in spi_qup_io_config()
715 controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
716 writel_relaxed(controller->n_words, in spi_qup_io_config()
717 controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
719 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
720 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
723 writel_relaxed(controller->n_words, in spi_qup_io_config()
724 controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
725 writel_relaxed(controller->n_words, in spi_qup_io_config()
726 controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
728 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
729 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
731 if (!controller->qup_v1) { in spi_qup_io_config()
734 input_cnt = controller->base + QUP_MX_INPUT_CNT; in spi_qup_io_config()
744 writel_relaxed(controller->n_words, input_cnt); in spi_qup_io_config()
746 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
750 reinit_completion(&controller->done); in spi_qup_io_config()
751 writel_relaxed(controller->n_words, in spi_qup_io_config()
752 controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
753 writel_relaxed(controller->n_words, in spi_qup_io_config()
754 controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
756 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
757 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
760 dev_err(controller->dev, "unknown mode = %d\n", in spi_qup_io_config()
761 controller->mode); in spi_qup_io_config()
765 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); in spi_qup_io_config()
769 if (!spi_qup_is_dma_xfer(controller->mode)) in spi_qup_io_config()
774 iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); in spi_qup_io_config()
775 iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); in spi_qup_io_config()
777 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES); in spi_qup_io_config()
779 control = readl_relaxed(controller->base + SPI_IO_CONTROL); in spi_qup_io_config()
786 writel_relaxed(control, controller->base + SPI_IO_CONTROL); in spi_qup_io_config()
788 config = readl_relaxed(controller->base + SPI_CONFIG); in spi_qup_io_config()
809 writel_relaxed(config, controller->base + SPI_CONFIG); in spi_qup_io_config()
811 config = readl_relaxed(controller->base + QUP_CONFIG); in spi_qup_io_config()
816 if (spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_io_config()
823 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_io_config()
826 if (!controller->qup_v1) { in spi_qup_io_config()
834 if (spi_qup_is_dma_xfer(controller->mode)) in spi_qup_io_config()
837 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK); in spi_qup_io_config()
847 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_transfer_one() local
860 reinit_completion(&controller->done); in spi_qup_transfer_one()
862 spin_lock_irqsave(&controller->lock, flags); in spi_qup_transfer_one()
863 controller->xfer = xfer; in spi_qup_transfer_one()
864 controller->error = 0; in spi_qup_transfer_one()
865 controller->rx_bytes = 0; in spi_qup_transfer_one()
866 controller->tx_bytes = 0; in spi_qup_transfer_one()
867 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_transfer_one()
869 if (spi_qup_is_dma_xfer(controller->mode)) in spi_qup_transfer_one()
874 spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_transfer_one()
875 spin_lock_irqsave(&controller->lock, flags); in spi_qup_transfer_one()
877 ret = controller->error; in spi_qup_transfer_one()
878 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_transfer_one()
880 if (ret && spi_qup_is_dma_xfer(controller->mode)) in spi_qup_transfer_one()
977 struct spi_qup *controller; in spi_qup_set_cs() local
981 controller = spi_controller_get_devdata(spi->controller); in spi_qup_set_cs()
982 spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL); in spi_qup_set_cs()
990 writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL); in spi_qup_set_cs()
997 struct spi_qup *controller; in spi_qup_probe() local
1057 controller = spi_controller_get_devdata(host); in spi_qup_probe()
1059 controller->dev = dev; in spi_qup_probe()
1060 controller->base = base; in spi_qup_probe()
1061 controller->iclk = iclk; in spi_qup_probe()
1062 controller->cclk = cclk; in spi_qup_probe()
1063 controller->irq = irq; in spi_qup_probe()
1071 controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev); in spi_qup_probe()
1073 if (!controller->qup_v1) in spi_qup_probe()
1076 spin_lock_init(&controller->lock); in spi_qup_probe()
1077 init_completion(&controller->done); in spi_qup_probe()
1096 controller->out_blk_sz = size * 16; in spi_qup_probe()
1098 controller->out_blk_sz = 4; in spi_qup_probe()
1102 controller->in_blk_sz = size * 16; in spi_qup_probe()
1104 controller->in_blk_sz = 4; in spi_qup_probe()
1107 controller->out_fifo_sz = controller->out_blk_sz * (2 << size); in spi_qup_probe()
1110 controller->in_fifo_sz = controller->in_blk_sz * (2 << size); in spi_qup_probe()
1113 controller->in_blk_sz, controller->in_fifo_sz, in spi_qup_probe()
1114 controller->out_blk_sz, controller->out_fifo_sz); in spi_qup_probe()
1118 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_probe()
1127 if (!controller->qup_v1) in spi_qup_probe()
1134 if (controller->qup_v1) in spi_qup_probe()
1143 IRQF_TRIGGER_HIGH, pdev->name, controller); in spi_qup_probe()
1174 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_pm_suspend_runtime() local
1178 config = readl(controller->base + QUP_CONFIG); in spi_qup_pm_suspend_runtime()
1180 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_pm_suspend_runtime()
1182 clk_disable_unprepare(controller->cclk); in spi_qup_pm_suspend_runtime()
1183 clk_disable_unprepare(controller->iclk); in spi_qup_pm_suspend_runtime()
1191 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_pm_resume_runtime() local
1195 ret = clk_prepare_enable(controller->iclk); in spi_qup_pm_resume_runtime()
1199 ret = clk_prepare_enable(controller->cclk); in spi_qup_pm_resume_runtime()
1201 clk_disable_unprepare(controller->iclk); in spi_qup_pm_resume_runtime()
1206 config = readl_relaxed(controller->base + QUP_CONFIG); in spi_qup_pm_resume_runtime()
1208 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_pm_resume_runtime()
1217 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_suspend() local
1229 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_suspend()
1233 clk_disable_unprepare(controller->cclk); in spi_qup_suspend()
1234 clk_disable_unprepare(controller->iclk); in spi_qup_suspend()
1241 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_resume() local
1244 ret = clk_prepare_enable(controller->iclk); in spi_qup_resume()
1248 ret = clk_prepare_enable(controller->cclk); in spi_qup_resume()
1250 clk_disable_unprepare(controller->iclk); in spi_qup_resume()
1254 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_resume()
1265 clk_disable_unprepare(controller->cclk); in spi_qup_resume()
1266 clk_disable_unprepare(controller->iclk); in spi_qup_resume()
1274 struct spi_qup *controller = spi_controller_get_devdata(host); in spi_qup_remove() local
1280 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_remove()
1282 dev_warn(&pdev->dev, "failed to reset controller (%pe)\n", in spi_qup_remove()
1285 clk_disable_unprepare(controller->cclk); in spi_qup_remove()
1286 clk_disable_unprepare(controller->iclk); in spi_qup_remove()