Lines Matching +full:pindir +full:- +full:d0 +full:- +full:out +full:- +full:d1 +full:- +full:in
1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
47 /* per-channel banks, 0x14 bytes each, first is: */
54 /* per-register bitmasks: */
151 writel_relaxed(val, mcspi->base + idx);
158 return readl_relaxed(mcspi->base + idx);
164 struct omap2_mcspi_cs *cs = spi->controller_state;
166 writel_relaxed(val, cs->base + idx);
171 struct omap2_mcspi_cs *cs = spi->controller_state;
173 return readl_relaxed(cs->base + idx);
178 struct omap2_mcspi_cs *cs = spi->controller_state;
180 return cs->chconf0;
185 struct omap2_mcspi_cs *cs = spi->controller_state;
187 cs->chconf0 = val;
224 struct omap2_mcspi_cs *cs = spi->controller_state;
227 l = cs->chctrl0;
232 cs->chctrl0 = l;
233 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
234 /* Flash post-writes */
240 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
247 if (spi->mode & SPI_CS_HIGH)
250 if (spi->controller_state) {
251 int err = pm_runtime_resume_and_get(mcspi->dev);
253 dev_err(mcspi->dev, "failed to get sync: %d\n", err);
266 pm_runtime_mark_last_busy(mcspi->dev);
267 pm_runtime_put_autosuspend(mcspi->dev);
274 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
290 ctx->modulctrl = l;
296 struct spi_controller *ctlr = spi->controller;
297 struct omap2_mcspi_cs *cs = spi->controller_state;
307 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
308 if (t->len % bytes_per_word != 0)
311 if (t->rx_buf != NULL && t->tx_buf != NULL)
316 wcnt = t->len / bytes_per_word;
321 if (t->rx_buf != NULL) {
323 xferlevel |= (bytes_per_word - 1) << 8;
326 if (t->tx_buf != NULL) {
328 xferlevel |= bytes_per_word - 1;
333 mcspi->fifo_depth = max_fifo_depth;
339 if (t->rx_buf != NULL)
342 if (t->tx_buf != NULL)
346 mcspi->fifo_depth = 0;
357 return -ETIMEDOUT;
369 if (spi_controller_is_target(mcspi->ctlr)) {
371 mcspi->target_aborted)
372 return -EINTR;
383 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
384 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
389 complete(&mcspi_dma->dma_rx_completion);
395 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
396 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
401 complete(&mcspi_dma->dma_tx_completion);
412 mcspi = spi_controller_get_devdata(spi->controller);
413 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
415 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
417 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
418 xfer->tx_sg.nents,
422 tx->callback = omap2_mcspi_tx_callback;
423 tx->callback_param = spi;
428 dma_async_issue_pending(mcspi_dma->dma_tx);
446 struct omap2_mcspi_cs *cs = spi->controller_state;
447 void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
450 mcspi = spi_controller_get_devdata(spi->controller);
451 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
452 count = xfer->len;
455 * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
456 * it mentions reducing DMA transfer length by one element in host
459 if (mcspi->fifo_depth == 0)
462 word_len = cs->word_len;
473 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
477 * configured in turbo mode.
479 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
484 sizes[0] = count - transfer_reduction;
496 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, 0, nb_sizes,
500 dev_err(&spi->dev, "sg_split failed\n");
504 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, sg_out[0],
508 tx->callback = omap2_mcspi_rx_callback;
509 tx->callback_param = spi;
515 dma_async_issue_pending(mcspi_dma->dma_rx);
518 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion);
519 if (ret || mcspi->target_aborted) {
520 dmaengine_terminate_sync(mcspi_dma->dma_rx);
528 if (mcspi->fifo_depth > 0)
537 elements = element_count - 1;
540 elements--;
548 ((u8 *)xfer->rx_buf)[elements++] = w;
550 ((u16 *)xfer->rx_buf)[elements++] = w;
552 ((u32 *)xfer->rx_buf)[elements++] = w;
555 dev_err(&spi->dev, "DMA RX penultimate word empty\n");
556 count -= (bytes_per_word << 1);
566 ((u8 *)xfer->rx_buf)[elements] = w;
568 ((u16 *)xfer->rx_buf)[elements] = w;
570 ((u32 *)xfer->rx_buf)[elements] = w;
572 dev_err(&spi->dev, "DMA RX last word empty\n");
573 count -= mcspi_bytes_per_word(word_len);
583 struct omap2_mcspi_cs *cs = spi->controller_state;
595 mcspi = spi_controller_get_devdata(spi->controller);
596 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
598 if (cs->word_len <= 8) {
601 } else if (cs->word_len <= 16) {
609 count = xfer->len;
612 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
613 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
619 rx = xfer->rx_buf;
620 tx = xfer->tx_buf;
622 mcspi->target_aborted = false;
623 reinit_completion(&mcspi_dma->dma_tx_completion);
624 reinit_completion(&mcspi_dma->dma_rx_completion);
625 reinit_completion(&mcspi->txdone);
627 /* Enable EOW IRQ to know end of tx in target mode */
628 if (spi_controller_is_target(spi->controller))
629 mcspi_write_reg(spi->controller,
641 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion);
642 if (ret || mcspi->target_aborted) {
643 dmaengine_terminate_sync(mcspi_dma->dma_tx);
648 if (spi_controller_is_target(mcspi->ctlr)) {
649 ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone);
650 if (ret || mcspi->target_aborted)
654 if (mcspi->fifo_depth > 0) {
655 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
659 dev_err(&spi->dev, "EOW timed out\n");
661 mcspi_write_reg(mcspi->ctlr, OMAP2_MCSPI_IRQSTATUS,
665 /* for TX_ONLY mode, be sure all words have shifted out */
667 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
668 if (mcspi->fifo_depth > 0) {
672 dev_err(&spi->dev, "TXFFE timed out\n");
677 dev_err(&spi->dev, "TXS timed out\n");
682 dev_err(&spi->dev, "EOT timed out\n");
691 struct omap2_mcspi_cs *cs = spi->controller_state;
694 void __iomem *base = cs->base;
700 count = xfer->len;
702 word_len = cs->word_len;
706 /* We store the pre-calculated register addresses on stack to speed
719 rx = xfer->rx_buf;
720 tx = xfer->tx_buf;
723 c -= 1;
727 dev_err(&spi->dev, "TXS timed out\n");
728 goto out;
730 dev_vdbg(&spi->dev, "write-%d %02x\n",
737 dev_err(&spi->dev, "RXS timed out\n");
738 goto out;
745 dev_vdbg(&spi->dev, "read-%d %02x\n",
746 word_len, *(rx - 1));
749 dev_err(&spi->dev,
750 "RXS timed out\n");
751 goto out;
759 dev_vdbg(&spi->dev, "read-%d %02x\n",
760 word_len, *(rx - 1));
763 spi_delay_exec(&xfer->word_delay, xfer);
769 rx = xfer->rx_buf;
770 tx = xfer->tx_buf;
772 c -= 2;
776 dev_err(&spi->dev, "TXS timed out\n");
777 goto out;
779 dev_vdbg(&spi->dev, "write-%d %04x\n",
786 dev_err(&spi->dev, "RXS timed out\n");
787 goto out;
794 dev_vdbg(&spi->dev, "read-%d %04x\n",
795 word_len, *(rx - 1));
798 dev_err(&spi->dev,
799 "RXS timed out\n");
800 goto out;
808 dev_vdbg(&spi->dev, "read-%d %04x\n",
809 word_len, *(rx - 1));
812 spi_delay_exec(&xfer->word_delay, xfer);
818 rx = xfer->rx_buf;
819 tx = xfer->tx_buf;
821 c -= 4;
825 dev_err(&spi->dev, "TXS timed out\n");
826 goto out;
828 dev_vdbg(&spi->dev, "write-%d %08x\n",
835 dev_err(&spi->dev, "RXS timed out\n");
836 goto out;
843 dev_vdbg(&spi->dev, "read-%d %08x\n",
844 word_len, *(rx - 1));
847 dev_err(&spi->dev,
848 "RXS timed out\n");
849 goto out;
857 dev_vdbg(&spi->dev, "read-%d %08x\n",
858 word_len, *(rx - 1));
861 spi_delay_exec(&xfer->word_delay, xfer);
865 /* for TX_ONLY mode, be sure all words have shifted out */
866 if (xfer->rx_buf == NULL) {
869 dev_err(&spi->dev, "TXS timed out\n");
872 dev_err(&spi->dev, "EOT timed out\n");
874 /* disable chan to purge rx datas received in TX_ONLY transfer,
880 out:
882 return count - c;
900 struct omap2_mcspi_cs *cs = spi->controller_state;
903 u8 word_len = spi->bits_per_word;
904 u32 speed_hz = spi->max_speed_hz;
906 mcspi = spi_controller_get_devdata(spi->controller);
908 if (t != NULL && t->bits_per_word)
909 word_len = t->bits_per_word;
911 cs->word_len = word_len;
913 if (t && t->speed_hz)
914 speed_hz = t->speed_hz;
916 ref_clk_hz = mcspi->ref_clk_hz;
923 div = (ref_clk_hz + speed_hz - 1) / speed_hz;
925 clkd = (div - 1) & 0xf;
926 extclk = (div - 1) >> 4;
932 /* standard 4-wire host mode: SCK, MOSI/out, MISO/in, nCS
935 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
947 l |= (word_len - 1) << 7;
950 if (!(spi->mode & SPI_CS_HIGH))
951 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
963 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
964 cs->chctrl0 |= extclk << 8;
965 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
969 if (spi->mode & SPI_CPOL)
973 if (spi->mode & SPI_CPHA)
980 cs->mode = spi->mode;
982 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
984 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
985 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
999 mcspi_dma->dma_rx = dma_request_chan(mcspi->dev,
1000 mcspi_dma->dma_rx_ch_name);
1001 if (IS_ERR(mcspi_dma->dma_rx)) {
1002 ret = PTR_ERR(mcspi_dma->dma_rx);
1003 mcspi_dma->dma_rx = NULL;
1007 mcspi_dma->dma_tx = dma_request_chan(mcspi->dev,
1008 mcspi_dma->dma_tx_ch_name);
1009 if (IS_ERR(mcspi_dma->dma_tx)) {
1010 ret = PTR_ERR(mcspi_dma->dma_tx);
1011 mcspi_dma->dma_tx = NULL;
1012 dma_release_channel(mcspi_dma->dma_rx);
1013 mcspi_dma->dma_rx = NULL;
1016 init_completion(&mcspi_dma->dma_rx_completion);
1017 init_completion(&mcspi_dma->dma_tx_completion);
1029 for (i = 0; i < ctlr->num_chipselect; i++) {
1030 mcspi_dma = &mcspi->dma_channels[i];
1032 if (mcspi_dma->dma_rx) {
1033 dma_release_channel(mcspi_dma->dma_rx);
1034 mcspi_dma->dma_rx = NULL;
1036 if (mcspi_dma->dma_tx) {
1037 dma_release_channel(mcspi_dma->dma_tx);
1038 mcspi_dma->dma_tx = NULL;
1047 if (spi->controller_state) {
1049 cs = spi->controller_state;
1050 list_del(&cs->node);
1060 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
1061 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1062 struct omap2_mcspi_cs *cs = spi->controller_state;
1067 return -ENOMEM;
1068 cs->base = mcspi->base + spi_get_chipselect(spi, 0) * 0x14;
1069 cs->phys = mcspi->phys + spi_get_chipselect(spi, 0) * 0x14;
1070 cs->mode = 0;
1071 cs->chconf0 = 0;
1072 cs->chctrl0 = 0;
1073 spi->controller_state = cs;
1075 list_add_tail(&cs->node, &ctx->cs);
1079 ret = pm_runtime_resume_and_get(mcspi->dev);
1091 pm_runtime_mark_last_busy(mcspi->dev);
1092 pm_runtime_put_autosuspend(mcspi->dev);
1102 irqstat = mcspi_read_reg(mcspi->ctlr, OMAP2_MCSPI_IRQSTATUS);
1107 mcspi_write_reg(mcspi->ctlr, OMAP2_MCSPI_IRQENABLE, 0);
1109 complete(&mcspi->txdone);
1117 struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels;
1119 mcspi->target_aborted = true;
1120 complete(&mcspi_dma->dma_rx_completion);
1121 complete(&mcspi_dma->dma_tx_completion);
1122 complete(&mcspi->txdone);
1132 /* We only enable one channel at a time -- the one whose message is
1133 * -- although this controller would gladly
1148 mcspi_dma = mcspi->dma_channels + spi_get_chipselect(spi, 0);
1149 cs = spi->controller_state;
1150 cd = spi->controller_data;
1153 * The target driver could have changed spi->mode in which case
1154 * it will be different from cs->mode (the current hardware setup).
1159 if (spi->mode != cs->mode)
1165 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1168 (t->speed_hz != spi->max_speed_hz) ||
1169 (t->bits_per_word != spi->bits_per_word)) {
1173 goto out;
1174 if (t->speed_hz == spi->max_speed_hz &&
1175 t->bits_per_word == spi->bits_per_word)
1178 if (cd && cd->cs_per_word) {
1179 chconf = mcspi->ctx.modulctrl;
1182 mcspi->ctx.modulctrl =
1190 if (t->tx_buf == NULL)
1192 else if (t->rx_buf == NULL)
1195 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1197 if (t->len > ((cs->word_len + 7) >> 3))
1203 if (t->len) {
1206 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1207 ctlr->cur_msg_mapped &&
1208 ctlr->can_dma(ctlr, spi, t))
1213 /* RX_ONLY mode needs dummy data in TX reg */
1214 if (t->tx_buf == NULL)
1215 writel_relaxed(0, cs->base
1218 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1219 ctlr->cur_msg_mapped &&
1220 ctlr->can_dma(ctlr, spi, t))
1225 if (count != t->len) {
1226 status = -EIO;
1227 goto out;
1233 if (mcspi->fifo_depth > 0)
1236 out:
1243 if (cd && cd->cs_per_word) {
1244 chconf = mcspi->ctx.modulctrl;
1247 mcspi->ctx.modulctrl =
1254 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1256 if (mcspi->fifo_depth > 0 && t)
1266 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1270 * in its chconf0 register.
1274 list_for_each_entry(cs, &ctx->cs, node) {
1275 if (msg->spi->controller_state == cs)
1278 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1279 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1280 writel_relaxed(cs->chconf0,
1281 cs->base + OMAP2_MCSPI_CHCONF0);
1282 readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1293 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
1295 &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
1297 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx)
1303 ctlr->dma_rx = mcspi_dma->dma_rx;
1304 ctlr->dma_tx = mcspi_dma->dma_tx;
1306 return (xfer->len >= DMA_MIN_BYTES);
1311 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
1313 &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
1315 if (mcspi->max_xfer_len && mcspi_dma->dma_rx)
1316 return mcspi->max_xfer_len;
1323 struct spi_controller *ctlr = mcspi->ctlr;
1324 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1327 ret = pm_runtime_resume_and_get(mcspi->dev);
1333 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1336 pm_runtime_mark_last_busy(mcspi->dev);
1337 pm_runtime_put_autosuspend(mcspi->dev);
1353 * When SPI wake up from off-mode, CS is in activate state. If it was in
1361 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1370 mcspi_write_reg(ctlr, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
1371 mcspi_write_reg(ctlr, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
1373 list_for_each_entry(cs, &ctx->cs, node) {
1376 * change in account.
1378 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1379 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1380 writel_relaxed(cs->chconf0,
1381 cs->base + OMAP2_MCSPI_CHCONF0);
1382 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1383 writel_relaxed(cs->chconf0,
1384 cs->base + OMAP2_MCSPI_CHCONF0);
1386 writel_relaxed(cs->chconf0,
1387 cs->base + OMAP2_MCSPI_CHCONF0);
1404 .max_xfer_len = SZ_4K - 1,
1409 .compatible = "ti,omap2-mcspi",
1413 .compatible = "ti,omap4-mcspi",
1417 .compatible = "ti,am654-mcspi",
1432 struct device_node *node = pdev->dev.of_node;
1435 if (of_property_read_bool(node, "spi-slave"))
1436 ctlr = spi_alloc_target(&pdev->dev, sizeof(*mcspi));
1438 ctlr = spi_alloc_host(&pdev->dev, sizeof(*mcspi));
1440 return -ENOMEM;
1442 /* the spi->mode bits understood by this driver: */
1443 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1444 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1445 ctlr->setup = omap2_mcspi_setup;
1446 ctlr->auto_runtime_pm = true;
1447 ctlr->prepare_message = omap2_mcspi_prepare_message;
1448 ctlr->can_dma = omap2_mcspi_can_dma;
1449 ctlr->transfer_one = omap2_mcspi_transfer_one;
1450 ctlr->set_cs = omap2_mcspi_set_cs;
1451 ctlr->cleanup = omap2_mcspi_cleanup;
1452 ctlr->target_abort = omap2_mcspi_target_abort;
1453 ctlr->dev.of_node = node;
1454 ctlr->use_gpio_descriptors = true;
1459 mcspi->ctlr = ctlr;
1461 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1464 pdata = match->data;
1466 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1467 ctlr->num_chipselect = num_cs;
1468 if (of_property_read_bool(node, "ti,pindir-d0-out-d1-in"))
1469 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1471 pdata = dev_get_platdata(&pdev->dev);
1472 ctlr->num_chipselect = pdata->num_cs;
1473 mcspi->pin_dir = pdata->pin_dir;
1475 regs_offset = pdata->regs_offset;
1476 if (pdata->max_xfer_len) {
1477 mcspi->max_xfer_len = pdata->max_xfer_len;
1478 ctlr->max_transfer_size = omap2_mcspi_max_xfer_size;
1481 mcspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
1482 if (IS_ERR(mcspi->base)) {
1483 status = PTR_ERR(mcspi->base);
1486 mcspi->phys = r->start + regs_offset;
1487 mcspi->base += regs_offset;
1489 mcspi->dev = &pdev->dev;
1491 INIT_LIST_HEAD(&mcspi->ctx.cs);
1493 mcspi->dma_channels = devm_kcalloc(&pdev->dev, ctlr->num_chipselect,
1496 if (mcspi->dma_channels == NULL) {
1497 status = -ENOMEM;
1501 for (i = 0; i < ctlr->num_chipselect; i++) {
1502 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
1503 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
1506 &mcspi->dma_channels[i]);
1507 if (status == -EPROBE_DEFER)
1514 init_completion(&mcspi->txdone);
1515 status = devm_request_irq(&pdev->dev, status,
1516 omap2_mcspi_irq_handler, 0, pdev->name,
1519 dev_err(&pdev->dev, "Cannot request IRQ");
1523 mcspi->ref_clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
1524 if (IS_ERR(mcspi->ref_clk))
1525 mcspi->ref_clk_hz = OMAP2_MCSPI_MAX_FREQ;
1527 mcspi->ref_clk_hz = clk_get_rate(mcspi->ref_clk);
1528 ctlr->max_speed_hz = mcspi->ref_clk_hz;
1529 ctlr->min_speed_hz = mcspi->ref_clk_hz >> 15;
1531 pm_runtime_use_autosuspend(&pdev->dev);
1532 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1533 pm_runtime_enable(&pdev->dev);
1539 status = devm_spi_register_controller(&pdev->dev, ctlr);
1546 pm_runtime_dont_use_autosuspend(&pdev->dev);
1547 pm_runtime_put_sync(&pdev->dev);
1548 pm_runtime_disable(&pdev->dev);
1562 pm_runtime_dont_use_autosuspend(mcspi->dev);
1563 pm_runtime_put_sync(mcspi->dev);
1564 pm_runtime_disable(&pdev->dev);
1578 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
1583 dev_warn(mcspi->dev, "%s: controller suspend failed: %i\n",
1597 dev_warn(mcspi->dev, "%s: controller resume failed: %i\n",