drivers/spi/spi-mxs.c

1 // SPDX-License-Identifier: GPL-2.0+
15 // Based on code from U-Boot bootloader by:
18 // Based on spi-stmp.c, which is:
28 #include <linux/dma-mapping.h>
40 #include <linux/spi/mxs-spi.h>
42 #include <linux/dma/mxs-dma.h>
44 #define DRIVER_NAME		"mxs-spi"
52  * Flags for txrx functions.  More efficient that using an argument register for
56 #define TXRX_DEASSERT_CS	(1<<1)	/* De-assert CS at end of txrx */
67 	struct mxs_spi *spi = spi_master_get_devdata(dev->master);
68 	struct mxs_ssp *ssp = &spi->ssp;
69 	const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
72 		dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
73 		return -EINVAL;
76 	if (hz != spi->sck) {
80 		 * ssp->clk_rate.  Otherwise we would set the rate every transfer
83 		spi->sck = hz;
91 		ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
95 	       ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
96 	       ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
97 	       ssp->base + HW_SSP_CTRL1(ssp));
99 	writel(0x0, ssp->base + HW_SSP_CMD0);
100 	writel(0x0, ssp->base + HW_SSP_CMD1);
115 	 * toggle the chip-select lines (nCS pins).
128 	struct mxs_ssp *ssp = &spi->ssp;
132 		reg = readl_relaxed(ssp->base + offset);
143 	return -ETIMEDOUT;
150 	complete(&spi->c);
157 	dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
159 		readl(ssp->base + HW_SSP_CTRL1(ssp)),
160 		readl(ssp->base + HW_SSP_STATUS(ssp)));
168 	struct mxs_ssp *ssp = &spi->ssp;
183 		return -EINVAL;
187 		return -ENOMEM;
189 	reinit_completion(&spi->c);
192 	ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
206 		 * De-assert CS on last segment if flag is set (i.e., no more
212 		if (ssp->devid == IMX23_SSP) {
218 		dma_xfer[sg_count].pio[3] = min;
223 				ret = -ENOMEM;
234 		ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
237 		len -= min;
241 		desc = dmaengine_prep_slave_sg(ssp->dmach,
243 				(ssp->devid == IMX23_SSP) ? 1 : 4,
247 			dev_err(ssp->dev,
249 			ret = -EINVAL;
253 		desc = dmaengine_prep_slave_sg(ssp->dmach,
259 			dev_err(ssp->dev,
261 			ret = -EINVAL;
270 	desc->callback = mxs_ssp_dma_irq_callback;
271 	desc->callback_param = spi;
275 	dma_async_issue_pending(ssp->dmach);
277 	if (!wait_for_completion_timeout(&spi->c,
279 		dev_err(ssp->dev, "DMA transfer timeout\n");
280 		ret = -ETIMEDOUT;
281 		dmaengine_terminate_all(ssp->dmach);
288 	while (--sg_count >= 0) {
290 		dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
303 	struct mxs_ssp *ssp = &spi->ssp;
306 	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
308 	while (len--) {
311 			       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
313 		if (ssp->devid == IMX23_SSP) {
315 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
317 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
319 			writel(1, ssp->base + HW_SSP_XFER_SIZE);
324 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
327 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
330 				ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
333 			return -ETIMEDOUT;
336 			writel(*buf, ssp->base + HW_SSP_DATA(ssp));
339 			     ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
344 				return -ETIMEDOUT;
346 			*buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
350 			return -ETIMEDOUT;
358 	return -ETIMEDOUT;
365 	struct mxs_ssp *ssp = &spi->ssp;
372 	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
373 	writel(mxs_spi_cs_to_reg(spi_get_chipselect(m->spi, 0)),
374 	       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
376 	list_for_each_entry(t, &m->transfers, transfer_list) {
380 		status = mxs_spi_setup_transfer(m->spi, t);
384 		/* De-assert on last transfer, inverted by cs_change flag */
385 		flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
397 		if (t->len < 32) {
399 				ssp->base + HW_SSP_CTRL1(ssp) +
402 			if (t->tx_buf)
404 						(void *)t->tx_buf,
405 						t->len, flag | TXRX_WRITE);
406 			if (t->rx_buf)
408 						t->rx_buf, t->len,
412 				ssp->base + HW_SSP_CTRL1(ssp) +
415 			if (t->tx_buf)
417 						(void *)t->tx_buf, t->len,
419 			if (t->rx_buf)
421 						t->rx_buf, t->len,
428 			stmp_reset_block(ssp->base);
432 		m->actual_length += t->len;
435 	m->status = status;
445 	struct mxs_ssp *ssp = &spi->ssp;
448 	clk_disable_unprepare(ssp->clk);
452 		int ret2 = clk_prepare_enable(ssp->clk);
466 	struct mxs_ssp *ssp = &spi->ssp;
473 	ret = clk_prepare_enable(ssp->clk);
521 	{ .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
522 	{ .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
530 			of_match_device(mxs_spi_dt_ids, &pdev->dev);
531 	struct device_node *np = pdev->dev.of_node;
543 	 * as a default. Override with "clock-frequency" DT prop.
555 	clk = devm_clk_get(&pdev->dev, NULL);
559 	devid = (enum mxs_ssp_id) of_id->data;
560 	ret = of_property_read_u32(np, "clock-frequency",
565 	master = spi_alloc_master(&pdev->dev, sizeof(*spi));
567 		return -ENOMEM;
571 	master->transfer_one_message = mxs_spi_transfer_one;
572 	master->bits_per_word_mask = SPI_BPW_MASK(8);
573 	master->mode_bits = SPI_CPOL | SPI_CPHA;
574 	master->num_chipselect = 3;
575 	master->dev.of_node = np;
576 	master->flags = SPI_CONTROLLER_HALF_DUPLEX;
577 	master->auto_runtime_pm = true;
580 	ssp = &spi->ssp;
581 	ssp->dev = &pdev->dev;
582 	ssp->clk = clk;
583 	ssp->base = base;
584 	ssp->devid = devid;
586 	init_completion(&spi->c);
588 	ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
589 			       dev_name(&pdev->dev), ssp);
593 	ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx");
594 	if (IS_ERR(ssp->dmach)) {
595 		dev_err(ssp->dev, "Failed to request DMA\n");
596 		ret = PTR_ERR(ssp->dmach);
600 	pm_runtime_enable(ssp->dev);
601 	if (!pm_runtime_enabled(ssp->dev)) {
602 		ret = mxs_spi_runtime_resume(ssp->dev);
604 			dev_err(ssp->dev, "runtime resume failed\n");
609 	ret = pm_runtime_resume_and_get(ssp->dev);
611 		dev_err(ssp->dev, "runtime_get_sync failed\n");
615 	clk_set_rate(ssp->clk, clk_freq);
617 	ret = stmp_reset_block(ssp->base);
621 	ret = devm_spi_register_master(&pdev->dev, master);
623 		dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
627 	pm_runtime_put(ssp->dev);
632 	pm_runtime_put(ssp->dev);
634 	pm_runtime_disable(ssp->dev);
636 	dma_release_channel(ssp->dmach);
650 	ssp = &spi->ssp;
652 	pm_runtime_disable(&pdev->dev);
653 	if (!pm_runtime_status_suspended(&pdev->dev))
654 		mxs_spi_runtime_suspend(&pdev->dev);
656 	dma_release_channel(ssp->dmach);
674 MODULE_ALIAS("platform:mxs-spi");