Lines Matching refs:mxic
191 static int mxic_spi_clk_enable(struct mxic_spi *mxic) in mxic_spi_clk_enable() argument
195 ret = clk_prepare_enable(mxic->send_clk); in mxic_spi_clk_enable()
199 ret = clk_prepare_enable(mxic->send_dly_clk); in mxic_spi_clk_enable()
206 clk_disable_unprepare(mxic->send_clk); in mxic_spi_clk_enable()
211 static void mxic_spi_clk_disable(struct mxic_spi *mxic) in mxic_spi_clk_disable() argument
213 clk_disable_unprepare(mxic->send_clk); in mxic_spi_clk_disable()
214 clk_disable_unprepare(mxic->send_dly_clk); in mxic_spi_clk_disable()
217 static void mxic_spi_set_input_delay_dqs(struct mxic_spi *mxic, u8 idly_code) in mxic_spi_set_input_delay_dqs() argument
223 mxic->regs + IDLY_CODE(0)); in mxic_spi_set_input_delay_dqs()
228 mxic->regs + IDLY_CODE(1)); in mxic_spi_set_input_delay_dqs()
231 static int mxic_spi_clk_setup(struct mxic_spi *mxic, unsigned long freq) in mxic_spi_clk_setup() argument
235 ret = clk_set_rate(mxic->send_clk, freq); in mxic_spi_clk_setup()
239 ret = clk_set_rate(mxic->send_dly_clk, freq); in mxic_spi_clk_setup()
247 mxic_spi_set_input_delay_dqs(mxic, 0xf); in mxic_spi_clk_setup()
257 ret = clk_set_phase(mxic->send_dly_clk, 9 * freq / 25000000); in mxic_spi_clk_setup()
264 static int mxic_spi_set_freq(struct mxic_spi *mxic, unsigned long freq) in mxic_spi_set_freq() argument
268 if (mxic->cur_speed_hz == freq) in mxic_spi_set_freq()
271 mxic_spi_clk_disable(mxic); in mxic_spi_set_freq()
272 ret = mxic_spi_clk_setup(mxic, freq); in mxic_spi_set_freq()
276 ret = mxic_spi_clk_enable(mxic); in mxic_spi_set_freq()
280 mxic->cur_speed_hz = freq; in mxic_spi_set_freq()
285 static void mxic_spi_hw_init(struct mxic_spi *mxic) in mxic_spi_hw_init() argument
287 writel(0, mxic->regs + DATA_STROB); in mxic_spi_hw_init()
288 writel(INT_STS_ALL, mxic->regs + INT_STS_EN); in mxic_spi_hw_init()
289 writel(0, mxic->regs + HC_EN); in mxic_spi_hw_init()
290 writel(0, mxic->regs + LRD_CFG); in mxic_spi_hw_init()
291 writel(0, mxic->regs + LRD_CTRL); in mxic_spi_hw_init()
294 mxic->regs + HC_CFG); in mxic_spi_hw_init()
342 static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf, in mxic_spi_data_xfer() argument
359 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, in mxic_spi_data_xfer()
364 writel(data, mxic->regs + TXD(nbytes % 4)); in mxic_spi_data_xfer()
366 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, in mxic_spi_data_xfer()
371 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, in mxic_spi_data_xfer()
377 data = readl(mxic->regs + RXD); in mxic_spi_data_xfer()
382 WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY); in mxic_spi_data_xfer()
393 struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master); in mxic_spi_mem_dirmap_read() local
400 writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); in mxic_spi_mem_dirmap_read()
403 mxic->regs + LRD_CFG); in mxic_spi_mem_dirmap_read()
404 writel(desc->info.offset + offs, mxic->regs + LRD_ADDR); in mxic_spi_mem_dirmap_read()
405 len = min_t(size_t, len, mxic->linear.size); in mxic_spi_mem_dirmap_read()
406 writel(len, mxic->regs + LRD_RANGE); in mxic_spi_mem_dirmap_read()
410 mxic->regs + LRD_CTRL); in mxic_spi_mem_dirmap_read()
412 if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) { in mxic_spi_mem_dirmap_read()
413 ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine, in mxic_spi_mem_dirmap_read()
415 mxic->linear.dma + offs); in mxic_spi_mem_dirmap_read()
419 memcpy_fromio(buf, mxic->linear.map, len); in mxic_spi_mem_dirmap_read()
422 writel(INT_LRD_DIS, mxic->regs + INT_STS); in mxic_spi_mem_dirmap_read()
423 writel(0, mxic->regs + LRD_CTRL); in mxic_spi_mem_dirmap_read()
425 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, in mxic_spi_mem_dirmap_read()
437 struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master); in mxic_spi_mem_dirmap_write() local
444 writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG); in mxic_spi_mem_dirmap_write()
447 mxic->regs + LWR_CFG); in mxic_spi_mem_dirmap_write()
448 writel(desc->info.offset + offs, mxic->regs + LWR_ADDR); in mxic_spi_mem_dirmap_write()
449 len = min_t(size_t, len, mxic->linear.size); in mxic_spi_mem_dirmap_write()
450 writel(len, mxic->regs + LWR_RANGE); in mxic_spi_mem_dirmap_write()
454 mxic->regs + LWR_CTRL); in mxic_spi_mem_dirmap_write()
456 if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) { in mxic_spi_mem_dirmap_write()
457 ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine, in mxic_spi_mem_dirmap_write()
459 mxic->linear.dma + offs); in mxic_spi_mem_dirmap_write()
463 memcpy_toio(mxic->linear.map, buf, len); in mxic_spi_mem_dirmap_write()
466 writel(INT_LWR_DIS, mxic->regs + INT_STS); in mxic_spi_mem_dirmap_write()
467 writel(0, mxic->regs + LWR_CTRL); in mxic_spi_mem_dirmap_write()
469 ret = readl_poll_timeout(mxic->regs + INT_STS, sts, in mxic_spi_mem_dirmap_write()
496 struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master); in mxic_spi_mem_dirmap_create() local
498 if (!mxic->linear.map) in mxic_spi_mem_dirmap_create()
513 struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master); in mxic_spi_mem_exec_op() local
517 ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz); in mxic_spi_mem_exec_op()
522 mxic->regs + HC_CFG); in mxic_spi_mem_exec_op()
524 writel(HC_EN_BIT, mxic->regs + HC_EN); in mxic_spi_mem_exec_op()
527 mxic->regs + SS_CTRL(spi_get_chipselect(mem->spi, 0))); in mxic_spi_mem_exec_op()
529 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, in mxic_spi_mem_exec_op()
530 mxic->regs + HC_CFG); in mxic_spi_mem_exec_op()
535 ret = mxic_spi_data_xfer(mxic, cmd, NULL, op->cmd.nbytes); in mxic_spi_mem_exec_op()
542 ret = mxic_spi_data_xfer(mxic, addr, NULL, op->addr.nbytes); in mxic_spi_mem_exec_op()
546 ret = mxic_spi_data_xfer(mxic, NULL, NULL, op->dummy.nbytes); in mxic_spi_mem_exec_op()
550 ret = mxic_spi_data_xfer(mxic, in mxic_spi_mem_exec_op()
558 writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT, in mxic_spi_mem_exec_op()
559 mxic->regs + HC_CFG); in mxic_spi_mem_exec_op()
560 writel(0, mxic->regs + HC_EN); in mxic_spi_mem_exec_op()
580 struct mxic_spi *mxic = spi_master_get_devdata(spi->master); in mxic_spi_set_cs() local
583 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_EN, in mxic_spi_set_cs()
584 mxic->regs + HC_CFG); in mxic_spi_set_cs()
585 writel(HC_EN_BIT, mxic->regs + HC_EN); in mxic_spi_set_cs()
586 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT, in mxic_spi_set_cs()
587 mxic->regs + HC_CFG); in mxic_spi_set_cs()
589 writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT, in mxic_spi_set_cs()
590 mxic->regs + HC_CFG); in mxic_spi_set_cs()
591 writel(0, mxic->regs + HC_EN); in mxic_spi_set_cs()
599 struct mxic_spi *mxic = spi_master_get_devdata(master); in mxic_spi_transfer_one() local
611 ret = mxic_spi_set_freq(mxic, t->speed_hz); in mxic_spi_transfer_one()
629 mxic->regs + SS_CTRL(0)); in mxic_spi_transfer_one()
631 ret = mxic_spi_data_xfer(mxic, t->tx_buf, t->rx_buf, t->len); in mxic_spi_transfer_one()
644 struct mxic_spi *mxic = nand->ecc.engine->priv; in mxic_spi_mem_ecc_init_ctx() local
646 mxic->ecc.use_pipelined_conf = true; in mxic_spi_mem_ecc_init_ctx()
654 struct mxic_spi *mxic = nand->ecc.engine->priv; in mxic_spi_mem_ecc_cleanup_ctx() local
656 mxic->ecc.use_pipelined_conf = false; in mxic_spi_mem_ecc_cleanup_ctx()
684 static void mxic_spi_mem_ecc_remove(struct mxic_spi *mxic) in mxic_spi_mem_ecc_remove() argument
686 if (mxic->ecc.pipelined_engine) { in mxic_spi_mem_ecc_remove()
687 mxic_ecc_put_pipelined_engine(mxic->ecc.pipelined_engine); in mxic_spi_mem_ecc_remove()
688 nand_ecc_unregister_on_host_hw_engine(mxic->ecc.pipelined_engine); in mxic_spi_mem_ecc_remove()
693 struct mxic_spi *mxic) in mxic_spi_mem_ecc_probe() argument
707 eng->priv = mxic; in mxic_spi_mem_ecc_probe()
708 mxic->ecc.pipelined_engine = eng; in mxic_spi_mem_ecc_probe()
717 struct mxic_spi *mxic = spi_master_get_devdata(master); in mxic_spi_runtime_suspend() local
719 mxic_spi_clk_disable(mxic); in mxic_spi_runtime_suspend()
720 clk_disable_unprepare(mxic->ps_clk); in mxic_spi_runtime_suspend()
728 struct mxic_spi *mxic = spi_master_get_devdata(master); in mxic_spi_runtime_resume() local
731 ret = clk_prepare_enable(mxic->ps_clk); in mxic_spi_runtime_resume()
737 return mxic_spi_clk_enable(mxic); in mxic_spi_runtime_resume()
749 struct mxic_spi *mxic; in mxic_spi_probe() local
758 mxic = spi_master_get_devdata(master); in mxic_spi_probe()
759 mxic->dev = &pdev->dev; in mxic_spi_probe()
763 mxic->ps_clk = devm_clk_get(&pdev->dev, "ps_clk"); in mxic_spi_probe()
764 if (IS_ERR(mxic->ps_clk)) in mxic_spi_probe()
765 return PTR_ERR(mxic->ps_clk); in mxic_spi_probe()
767 mxic->send_clk = devm_clk_get(&pdev->dev, "send_clk"); in mxic_spi_probe()
768 if (IS_ERR(mxic->send_clk)) in mxic_spi_probe()
769 return PTR_ERR(mxic->send_clk); in mxic_spi_probe()
771 mxic->send_dly_clk = devm_clk_get(&pdev->dev, "send_dly_clk"); in mxic_spi_probe()
772 if (IS_ERR(mxic->send_dly_clk)) in mxic_spi_probe()
773 return PTR_ERR(mxic->send_dly_clk); in mxic_spi_probe()
775 mxic->regs = devm_platform_ioremap_resource_byname(pdev, "regs"); in mxic_spi_probe()
776 if (IS_ERR(mxic->regs)) in mxic_spi_probe()
777 return PTR_ERR(mxic->regs); in mxic_spi_probe()
780 mxic->linear.map = devm_ioremap_resource(&pdev->dev, res); in mxic_spi_probe()
781 if (!IS_ERR(mxic->linear.map)) { in mxic_spi_probe()
782 mxic->linear.dma = res->start; in mxic_spi_probe()
783 mxic->linear.size = resource_size(res); in mxic_spi_probe()
785 mxic->linear.map = NULL; in mxic_spi_probe()
803 mxic_spi_hw_init(mxic); in mxic_spi_probe()
805 ret = mxic_spi_mem_ecc_probe(pdev, mxic); in mxic_spi_probe()
815 mxic_spi_mem_ecc_remove(mxic); in mxic_spi_probe()
824 struct mxic_spi *mxic = spi_master_get_devdata(master); in mxic_spi_remove() local
827 mxic_spi_mem_ecc_remove(mxic); in mxic_spi_remove()