Lines Matching refs:reg_val
271 u32 reg_val; in mtk_spi_reset() local
274 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
275 reg_val |= SPI_CMD_RST; in mtk_spi_reset()
276 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
278 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
279 reg_val &= ~SPI_CMD_RST; in mtk_spi_reset()
280 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
290 u32 reg_val; in mtk_spi_set_hw_cs_timing() local
309 reg_val = readl(mdata->base + SPI_CFG0_REG); in mtk_spi_set_hw_cs_timing()
313 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing()
314 reg_val |= (((hold - 1) & 0xffff) in mtk_spi_set_hw_cs_timing()
319 reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); in mtk_spi_set_hw_cs_timing()
320 reg_val |= (((setup - 1) & 0xffff) in mtk_spi_set_hw_cs_timing()
326 reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing()
327 reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing()
331 reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET); in mtk_spi_set_hw_cs_timing()
332 reg_val |= (((setup - 1) & 0xff) in mtk_spi_set_hw_cs_timing()
336 writel(reg_val, mdata->base + SPI_CFG0_REG); in mtk_spi_set_hw_cs_timing()
341 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_set_hw_cs_timing()
342 reg_val &= ~SPI_CFG1_CS_IDLE_MASK; in mtk_spi_set_hw_cs_timing()
343 reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); in mtk_spi_set_hw_cs_timing()
344 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_set_hw_cs_timing()
354 u32 reg_val; in mtk_spi_hw_init() local
361 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_hw_init()
364 reg_val |= SPI_CMD_IPM_NONIDLE_MODE; in mtk_spi_hw_init()
366 reg_val |= SPI_CMD_IPM_SPIM_LOOP; in mtk_spi_hw_init()
368 reg_val &= ~SPI_CMD_IPM_SPIM_LOOP; in mtk_spi_hw_init()
372 reg_val |= SPI_CMD_CPHA; in mtk_spi_hw_init()
374 reg_val &= ~SPI_CMD_CPHA; in mtk_spi_hw_init()
376 reg_val |= SPI_CMD_CPOL; in mtk_spi_hw_init()
378 reg_val &= ~SPI_CMD_CPOL; in mtk_spi_hw_init()
382 reg_val &= ~SPI_CMD_TXMSBF; in mtk_spi_hw_init()
383 reg_val &= ~SPI_CMD_RXMSBF; in mtk_spi_hw_init()
385 reg_val |= SPI_CMD_TXMSBF; in mtk_spi_hw_init()
386 reg_val |= SPI_CMD_RXMSBF; in mtk_spi_hw_init()
391 reg_val &= ~SPI_CMD_TX_ENDIAN; in mtk_spi_hw_init()
392 reg_val &= ~SPI_CMD_RX_ENDIAN; in mtk_spi_hw_init()
394 reg_val |= SPI_CMD_TX_ENDIAN; in mtk_spi_hw_init()
395 reg_val |= SPI_CMD_RX_ENDIAN; in mtk_spi_hw_init()
401 reg_val |= SPI_CMD_CS_POL; in mtk_spi_hw_init()
403 reg_val &= ~SPI_CMD_CS_POL; in mtk_spi_hw_init()
406 reg_val |= SPI_CMD_SAMPLE_SEL; in mtk_spi_hw_init()
408 reg_val &= ~SPI_CMD_SAMPLE_SEL; in mtk_spi_hw_init()
412 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE; in mtk_spi_hw_init()
415 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); in mtk_spi_hw_init()
418 reg_val &= ~SPI_CMD_DEASSERT; in mtk_spi_hw_init()
420 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_hw_init()
430 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_hw_init()
431 reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; in mtk_spi_hw_init()
432 reg_val |= ((chip_config->tick_delay & 0x7) in mtk_spi_hw_init()
434 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_hw_init()
436 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_hw_init()
437 reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; in mtk_spi_hw_init()
438 reg_val |= ((chip_config->tick_delay & 0x7) in mtk_spi_hw_init()
440 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_hw_init()
443 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_hw_init()
444 reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; in mtk_spi_hw_init()
445 reg_val |= ((chip_config->tick_delay & 0x3) in mtk_spi_hw_init()
447 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_hw_init()
463 u32 reg_val; in mtk_spi_set_cs() local
469 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
471 reg_val |= SPI_CMD_PAUSE_EN; in mtk_spi_set_cs()
472 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
474 reg_val &= ~SPI_CMD_PAUSE_EN; in mtk_spi_set_cs()
475 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
484 u32 div, sck_time, reg_val; in mtk_spi_prepare_transfer() local
495 reg_val = readl(mdata->base + SPI_CFG2_REG); in mtk_spi_prepare_transfer()
496 reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET); in mtk_spi_prepare_transfer()
497 reg_val |= (((sck_time - 1) & 0xffff) in mtk_spi_prepare_transfer()
499 reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET); in mtk_spi_prepare_transfer()
500 reg_val |= (((sck_time - 1) & 0xffff) in mtk_spi_prepare_transfer()
502 writel(reg_val, mdata->base + SPI_CFG2_REG); in mtk_spi_prepare_transfer()
504 reg_val = readl(mdata->base + SPI_CFG0_REG); in mtk_spi_prepare_transfer()
505 reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET); in mtk_spi_prepare_transfer()
506 reg_val |= (((sck_time - 1) & 0xff) in mtk_spi_prepare_transfer()
508 reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET); in mtk_spi_prepare_transfer()
509 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); in mtk_spi_prepare_transfer()
510 writel(reg_val, mdata->base + SPI_CFG0_REG); in mtk_spi_prepare_transfer()
516 u32 packet_size, packet_loop, reg_val; in mtk_spi_setup_packet() local
530 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_setup_packet()
532 reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK; in mtk_spi_setup_packet()
534 reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK; in mtk_spi_setup_packet()
535 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; in mtk_spi_setup_packet()
536 reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK; in mtk_spi_setup_packet()
537 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; in mtk_spi_setup_packet()
538 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_setup_packet()
628 u32 reg_val; in mtk_spi_fifo_transfer() local
642 reg_val = 0; in mtk_spi_fifo_transfer()
643 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder); in mtk_spi_fifo_transfer()
644 writel(reg_val, mdata->base + SPI_TX_DATA_REG); in mtk_spi_fifo_transfer()
703 u32 reg_val = 0; in mtk_spi_transfer_one() local
708 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; in mtk_spi_transfer_one()
710 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; in mtk_spi_transfer_one()
712 writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); in mtk_spi_transfer_one()
747 u32 cmd, reg_val, cnt, remainder, len; in mtk_spi_interrupt() local
752 reg_val = readl(mdata->base + SPI_STATUS0_REG); in mtk_spi_interrupt()
753 if (reg_val & MTK_SPI_PAUSE_INT_STATUS) in mtk_spi_interrupt()
771 reg_val = readl(mdata->base + SPI_RX_DATA_REG); in mtk_spi_interrupt()
775 ®_val, in mtk_spi_interrupt()
797 reg_val = 0; in mtk_spi_interrupt()
798 memcpy(®_val, in mtk_spi_interrupt()
801 writel(reg_val, mdata->base + SPI_TX_DATA_REG); in mtk_spi_interrupt()
947 u32 reg_val, nio, tx_size; in mtk_spi_mem_exec_op() local
958 reg_val = readl(mdata->base + SPI_CFG3_IPM_REG); in mtk_spi_mem_exec_op()
960 reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK; in mtk_spi_mem_exec_op()
961 reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET; in mtk_spi_mem_exec_op()
964 reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK; in mtk_spi_mem_exec_op()
966 reg_val |= (op->addr.nbytes + op->dummy.nbytes) << in mtk_spi_mem_exec_op()
971 reg_val |= SPI_CFG3_IPM_NODATA_FLAG; in mtk_spi_mem_exec_op()
974 reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG; in mtk_spi_mem_exec_op()
981 reg_val |= SPI_CFG3_IPM_XMODE_EN; in mtk_spi_mem_exec_op()
983 reg_val &= ~SPI_CFG3_IPM_XMODE_EN; in mtk_spi_mem_exec_op()
997 reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK; in mtk_spi_mem_exec_op()
998 reg_val |= PIN_MODE_CFG(nio); in mtk_spi_mem_exec_op()
1000 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; in mtk_spi_mem_exec_op()
1002 reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; in mtk_spi_mem_exec_op()
1004 reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR; in mtk_spi_mem_exec_op()
1005 writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); in mtk_spi_mem_exec_op()
1068 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_mem_exec_op()
1069 reg_val |= SPI_CMD_TX_DMA; in mtk_spi_mem_exec_op()
1071 reg_val |= SPI_CMD_RX_DMA; in mtk_spi_mem_exec_op()
1072 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_mem_exec_op()
1084 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_mem_exec_op()
1085 reg_val &= ~SPI_CMD_TX_DMA; in mtk_spi_mem_exec_op()
1087 reg_val &= ~SPI_CMD_RX_DMA; in mtk_spi_mem_exec_op()
1088 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_mem_exec_op()