3  * MPC52xx PSC in SPI mode driver.
26 #define MCLK 20000000 /* PSC port MClk in hz */
30 	struct mpc52xx_psc __iomem *psc;  member
64 	struct mpc52xx_psc __iomem *psc = mps->psc;  in mpc52xx_psc_spi_activate_cs()  local
68 	sicr = in_be32(&psc->sicr);  in mpc52xx_psc_spi_activate_cs()
84 	out_be32(&psc->sicr, sicr);  in mpc52xx_psc_spi_activate_cs()
87 	 * Because psc->ccr is defined as 16bit register instead of 32bit  in mpc52xx_psc_spi_activate_cs()
90 	ccr = in_be16((u16 __iomem *)&psc->ccr);  in mpc52xx_psc_spi_activate_cs()
96 	out_be16((u16 __iomem *)&psc->ccr, ccr);  in mpc52xx_psc_spi_activate_cs()
108 	struct mpc52xx_psc __iomem *psc = mps->psc;  in mpc52xx_psc_spi_transfer_rxtx()  local
123 	out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);  in mpc52xx_psc_spi_transfer_rxtx()
138 				out_8(&psc->ircr2, 0x01);  in mpc52xx_psc_spi_transfer_rxtx()
141 				out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);  in mpc52xx_psc_spi_transfer_rxtx()
143 				out_8(&psc->mpc52xx_psc_buffer_8, 0);  in mpc52xx_psc_spi_transfer_rxtx()
151 		out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);  in mpc52xx_psc_spi_transfer_rxtx()
153 			out_8(&psc->mode, 0);  in mpc52xx_psc_spi_transfer_rxtx()
155 			out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);  in mpc52xx_psc_spi_transfer_rxtx()
158 		out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);  in mpc52xx_psc_spi_transfer_rxtx()
166 				rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);  in mpc52xx_psc_spi_transfer_rxtx()
169 				in_8(&psc->mpc52xx_psc_buffer_8);  in mpc52xx_psc_spi_transfer_rxtx()
173 	out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);  in mpc52xx_psc_spi_transfer_rxtx()
244 	struct mpc52xx_psc __iomem *psc = mps->psc;  in mpc52xx_psc_spi_port_config()  local
255 	/* Reset the PSC into a known state */  in mpc52xx_psc_spi_port_config()
256 	out_8(&psc->command, MPC52xx_PSC_RST_RX);  in mpc52xx_psc_spi_port_config()
257 	out_8(&psc->command, MPC52xx_PSC_RST_TX);  in mpc52xx_psc_spi_port_config()
258 	out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);  in mpc52xx_psc_spi_port_config()
261 	out_be16(&psc->mpc52xx_psc_imr, 0);  in mpc52xx_psc_spi_port_config()
262 	out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);  in mpc52xx_psc_spi_port_config()
264 	out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);  in mpc52xx_psc_spi_port_config()
268 	out_be32(&psc->sicr, 0x0180C800);  in mpc52xx_psc_spi_port_config()
269 	out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */  in mpc52xx_psc_spi_port_config()
272 	out_8(&psc->ctur, 0x00);  in mpc52xx_psc_spi_port_config()
273 	out_8(&psc->ctlr, 0x84);  in mpc52xx_psc_spi_port_config()
283 	struct mpc52xx_psc __iomem *psc = mps->psc;  in mpc52xx_psc_spi_isr()  local
286 	if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {  in mpc52xx_psc_spi_isr()
287 		out_be16(&psc->mpc52xx_psc_imr, 0);  in mpc52xx_psc_spi_isr()
324 	mps->psc = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);  in mpc52xx_psc_spi_of_probe()
325 	if (IS_ERR(mps->psc))  in mpc52xx_psc_spi_of_probe()
326 		return dev_err_probe(dev, PTR_ERR(mps->psc), "could not ioremap I/O port range\n");  in mpc52xx_psc_spi_of_probe()
328 	/* On the 5200, fifo regs are immediately ajacent to the psc regs */  in mpc52xx_psc_spi_of_probe()
329 	mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);  in mpc52xx_psc_spi_of_probe()
336 			       "mpc52xx-psc-spi", mps);  in mpc52xx_psc_spi_of_probe()
342 		return dev_err_probe(dev, ret, "can't configure PSC! Is it capable of SPI?\n");  in mpc52xx_psc_spi_of_probe()
350 	{ .compatible = "fsl,mpc5200-psc-spi", },
351 	{ .compatible = "mpc5200-psc-spi", }, /* old */
360 		.name = "mpc52xx-psc-spi",
367 MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");