Lines Matching full:reg_base
93 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_change_mode() local
94 __be32 __iomem *mode = ®_base->mode; in fsl_spi_change_mode()
238 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_bufs() local
243 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); in fsl_spi_cpu_bufs()
247 mpc8xxx_spi_write_reg(®_base->transmit, word); in fsl_spi_cpu_bufs()
256 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_bufs() local
261 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_bufs()
286 mpc8xxx_spi_write_reg(®_base->mask, 0); in fsl_spi_bufs()
372 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_setup() local
390 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_setup()
393 cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); in fsl_spi_setup()
428 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_irq() local
432 u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); in fsl_spi_cpu_irq()
441 mpc8xxx_spi_read_reg(®_base->event)) & in fsl_spi_cpu_irq()
446 mpc8xxx_spi_write_reg(®_base->event, events); in fsl_spi_cpu_irq()
452 mpc8xxx_spi_write_reg(®_base->transmit, word); in fsl_spi_cpu_irq()
463 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_irq() local
466 events = mpc8xxx_spi_read_reg(®_base->event); in fsl_spi_irq()
483 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_cs_control() local
488 slvsel = mpc8xxx_spi_read_reg(®_base->slvsel); in fsl_spi_grlib_cs_control()
490 mpc8xxx_spi_write_reg(®_base->slvsel, slvsel); in fsl_spi_grlib_cs_control()
498 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_probe() local
502 capabilities = mpc8xxx_spi_read_reg(®_base->cap); in fsl_spi_grlib_probe()
512 mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff); in fsl_spi_grlib_probe()
535 struct fsl_spi_reg __iomem *reg_base; in fsl_spi_probe() local
565 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); in fsl_spi_probe()
566 if (IS_ERR(mpc8xxx_spi->reg_base)) { in fsl_spi_probe()
567 ret = PTR_ERR(mpc8xxx_spi->reg_base); in fsl_spi_probe()
599 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_probe()
602 mpc8xxx_spi_write_reg(®_base->mode, 0); in fsl_spi_probe()
603 mpc8xxx_spi_write_reg(®_base->mask, 0); in fsl_spi_probe()
604 mpc8xxx_spi_write_reg(®_base->command, 0); in fsl_spi_probe()
605 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); in fsl_spi_probe()
616 mpc8xxx_spi_write_reg(®_base->mode, regval); in fsl_spi_probe()
622 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, in fsl_spi_probe()