277 static inline int needs_swap_endian(struct fsl_qspi *q)  in needs_swap_endian()  argument
279 	return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;  in needs_swap_endian()
282 static inline int needs_4x_clock(struct fsl_qspi *q)  in needs_4x_clock()  argument
284 	return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;  in needs_4x_clock()
287 static inline int needs_fill_txfifo(struct fsl_qspi *q)  in needs_fill_txfifo()  argument
289 	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;  in needs_fill_txfifo()
292 static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)  in needs_wakeup_wait_mode()  argument
294 	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;  in needs_wakeup_wait_mode()
297 static inline int needs_amba_base_offset(struct fsl_qspi *q)  in needs_amba_base_offset()  argument
299 	return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);  in needs_amba_base_offset()
302 static inline int needs_tdh_setting(struct fsl_qspi *q)  in needs_tdh_setting()  argument
304 	return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;  in needs_tdh_setting()
311 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)  in fsl_qspi_endian_xchg()  argument
313 	return needs_swap_endian(q) ? __swab32(a) : a;  in fsl_qspi_endian_xchg()
323 static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)  in qspi_writel()  argument
325 	if (q->devtype_data->little_endian)  in qspi_writel()
331 static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)  in qspi_readl()  argument
333 	if (q->devtype_data->little_endian)  in qspi_readl()
341 	struct fsl_qspi *q = dev_id;  in fsl_qspi_irq_handler()  local
345 	reg = qspi_readl(q, q->iobase + QUADSPI_FR);  in fsl_qspi_irq_handler()
346 	qspi_writel(q, reg, q->iobase + QUADSPI_FR);  in fsl_qspi_irq_handler()
349 		complete(&q->c);  in fsl_qspi_irq_handler()
351 	dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg);  in fsl_qspi_irq_handler()
355 static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)  in fsl_qspi_check_buswidth()  argument
370 	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller);  in fsl_qspi_supports_op()  local
373 	ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);  in fsl_qspi_supports_op()
376 		ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);  in fsl_qspi_supports_op()
379 		ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);  in fsl_qspi_supports_op()
382 		ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);  in fsl_qspi_supports_op()
403 	    (op->data.nbytes > q->devtype_data->ahb_buf_size ||  in fsl_qspi_supports_op()
404 	     (op->data.nbytes > q->devtype_data->rxfifo - 4 &&  in fsl_qspi_supports_op()
409 	    op->data.nbytes > q->devtype_data->txfifo)  in fsl_qspi_supports_op()
415 static void fsl_qspi_prepare_lut(struct fsl_qspi *q,  in fsl_qspi_prepare_lut()  argument
418 	void __iomem *base = q->iobase;  in fsl_qspi_prepare_lut()
459 	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);  in fsl_qspi_prepare_lut()
460 	qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);  in fsl_qspi_prepare_lut()
464 		qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));  in fsl_qspi_prepare_lut()
467 	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);  in fsl_qspi_prepare_lut()
468 	qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);  in fsl_qspi_prepare_lut()
471 static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)  in fsl_qspi_clk_prep_enable()  argument
475 	ret = clk_prepare_enable(q->clk_en);  in fsl_qspi_clk_prep_enable()
479 	ret = clk_prepare_enable(q->clk);  in fsl_qspi_clk_prep_enable()
481 		clk_disable_unprepare(q->clk_en);  in fsl_qspi_clk_prep_enable()
485 	if (needs_wakeup_wait_mode(q))  in fsl_qspi_clk_prep_enable()
486 		cpu_latency_qos_add_request(&q->pm_qos_req, 0);  in fsl_qspi_clk_prep_enable()
491 static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)  in fsl_qspi_clk_disable_unprep()  argument
493 	if (needs_wakeup_wait_mode(q))  in fsl_qspi_clk_disable_unprep()
494 		cpu_latency_qos_remove_request(&q->pm_qos_req);  in fsl_qspi_clk_disable_unprep()
496 	clk_disable_unprepare(q->clk);  in fsl_qspi_clk_disable_unprep()
497 	clk_disable_unprepare(q->clk_en);  in fsl_qspi_clk_disable_unprep()
507 static void fsl_qspi_invalidate(struct fsl_qspi *q)  in fsl_qspi_invalidate()  argument
511 	reg = qspi_readl(q, q->iobase + QUADSPI_MCR);  in fsl_qspi_invalidate()
513 	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);  in fsl_qspi_invalidate()
522 	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);  in fsl_qspi_invalidate()
525 static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi)  in fsl_qspi_select_mem()  argument
530 	if (q->selected == spi_get_chipselect(spi, 0))  in fsl_qspi_select_mem()
533 	if (needs_4x_clock(q))  in fsl_qspi_select_mem()
536 	fsl_qspi_clk_disable_unprep(q);  in fsl_qspi_select_mem()
538 	ret = clk_set_rate(q->clk, rate);  in fsl_qspi_select_mem()
542 	ret = fsl_qspi_clk_prep_enable(q);  in fsl_qspi_select_mem()
546 	q->selected = spi_get_chipselect(spi, 0);  in fsl_qspi_select_mem()
548 	fsl_qspi_invalidate(q);  in fsl_qspi_select_mem()
551 static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)  in fsl_qspi_read_ahb()  argument
554 		      q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,  in fsl_qspi_read_ahb()
558 static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,  in fsl_qspi_fill_txfifo()  argument
561 	void __iomem *base = q->iobase;  in fsl_qspi_fill_txfifo()
567 		val = fsl_qspi_endian_xchg(q, val);  in fsl_qspi_fill_txfifo()
568 		qspi_writel(q, val, base + QUADSPI_TBDR);  in fsl_qspi_fill_txfifo()
573 		val = fsl_qspi_endian_xchg(q, val);  in fsl_qspi_fill_txfifo()
574 		qspi_writel(q, val, base + QUADSPI_TBDR);  in fsl_qspi_fill_txfifo()
577 	if (needs_fill_txfifo(q)) {  in fsl_qspi_fill_txfifo()
579 			qspi_writel(q, 0, base + QUADSPI_TBDR);  in fsl_qspi_fill_txfifo()
583 static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,  in fsl_qspi_read_rxfifo()  argument
586 	void __iomem *base = q->iobase;  in fsl_qspi_read_rxfifo()
592 		val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));  in fsl_qspi_read_rxfifo()
593 		val = fsl_qspi_endian_xchg(q, val);  in fsl_qspi_read_rxfifo()
598 		val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));  in fsl_qspi_read_rxfifo()
599 		val = fsl_qspi_endian_xchg(q, val);  in fsl_qspi_read_rxfifo()
604 static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)  in fsl_qspi_do_op()  argument
606 	void __iomem *base = q->iobase;  in fsl_qspi_do_op()
609 	init_completion(&q->c);  in fsl_qspi_do_op()
616 	qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),  in fsl_qspi_do_op()
620 	if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000)))  in fsl_qspi_do_op()
624 		fsl_qspi_read_rxfifo(q, op);  in fsl_qspi_do_op()
629 static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,  in fsl_qspi_readl_poll_tout()  argument
634 	if (!q->devtype_data->little_endian)  in fsl_qspi_readl_poll_tout()
643 	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller);  in fsl_qspi_exec_op()  local
644 	void __iomem *base = q->iobase;  in fsl_qspi_exec_op()
647 	int invalid_mstrid = q->devtype_data->invalid_mstrid;  in fsl_qspi_exec_op()
649 	mutex_lock(&q->lock);  in fsl_qspi_exec_op()
652 	fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |  in fsl_qspi_exec_op()
655 	fsl_qspi_select_mem(q, mem->spi);  in fsl_qspi_exec_op()
657 	if (needs_amba_base_offset(q))  in fsl_qspi_exec_op()
658 		addr_offset = q->memmap_phy;  in fsl_qspi_exec_op()
660 	qspi_writel(q,  in fsl_qspi_exec_op()
661 		    q->selected * q->devtype_data->ahb_buf_size + addr_offset,  in fsl_qspi_exec_op()
664 	qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |  in fsl_qspi_exec_op()
668 	qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,  in fsl_qspi_exec_op()
671 	qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF0CR);  in fsl_qspi_exec_op()
672 	qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF1CR);  in fsl_qspi_exec_op()
673 	qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF2CR);  in fsl_qspi_exec_op()
675 	fsl_qspi_prepare_lut(q, op);  in fsl_qspi_exec_op()
682 	if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&  in fsl_qspi_exec_op()
684 		fsl_qspi_read_ahb(q, op);  in fsl_qspi_exec_op()
686 		qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |  in fsl_qspi_exec_op()
690 			fsl_qspi_fill_txfifo(q, op);  in fsl_qspi_exec_op()
692 		err = fsl_qspi_do_op(q, op);  in fsl_qspi_exec_op()
696 	fsl_qspi_invalidate(q);  in fsl_qspi_exec_op()
698 	mutex_unlock(&q->lock);  in fsl_qspi_exec_op()
705 	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller);  in fsl_qspi_adjust_op_size()  local
708 		if (op->data.nbytes > q->devtype_data->txfifo)  in fsl_qspi_adjust_op_size()
709 			op->data.nbytes = q->devtype_data->txfifo;  in fsl_qspi_adjust_op_size()
711 		if (op->data.nbytes > q->devtype_data->ahb_buf_size)  in fsl_qspi_adjust_op_size()
712 			op->data.nbytes = q->devtype_data->ahb_buf_size;  in fsl_qspi_adjust_op_size()
713 		else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))  in fsl_qspi_adjust_op_size()
720 static int fsl_qspi_default_setup(struct fsl_qspi *q)  in fsl_qspi_default_setup()  argument
722 	void __iomem *base = q->iobase;  in fsl_qspi_default_setup()
727 	fsl_qspi_clk_disable_unprep(q);  in fsl_qspi_default_setup()
730 	ret = clk_set_rate(q->clk, 66000000);  in fsl_qspi_default_setup()
734 	ret = fsl_qspi_clk_prep_enable(q);  in fsl_qspi_default_setup()
739 	qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,  in fsl_qspi_default_setup()
744 	qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,  in fsl_qspi_default_setup()
752 	if (needs_tdh_setting(q))  in fsl_qspi_default_setup()
753 		qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &  in fsl_qspi_default_setup()
757 	reg = qspi_readl(q, base + QUADSPI_SMPR);  in fsl_qspi_default_setup()
758 	qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK  in fsl_qspi_default_setup()
764 	qspi_writel(q, 0, base + QUADSPI_BUF0IND);  in fsl_qspi_default_setup()
765 	qspi_writel(q, 0, base + QUADSPI_BUF1IND);  in fsl_qspi_default_setup()
766 	qspi_writel(q, 0, base + QUADSPI_BUF2IND);  in fsl_qspi_default_setup()
768 	qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),  in fsl_qspi_default_setup()
769 		    q->iobase + QUADSPI_BFGENCR);  in fsl_qspi_default_setup()
770 	qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);  in fsl_qspi_default_setup()
771 	qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |  in fsl_qspi_default_setup()
772 		    QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),  in fsl_qspi_default_setup()
775 	if (needs_amba_base_offset(q))  in fsl_qspi_default_setup()
776 		addr_offset = q->memmap_phy;  in fsl_qspi_default_setup()
785 	qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,  in fsl_qspi_default_setup()
787 	qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,  in fsl_qspi_default_setup()
789 	qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,  in fsl_qspi_default_setup()
791 	qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,  in fsl_qspi_default_setup()
794 	q->selected = -1;  in fsl_qspi_default_setup()
797 	qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,  in fsl_qspi_default_setup()
801 	qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);  in fsl_qspi_default_setup()
804 	qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);  in fsl_qspi_default_setup()
811 	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->controller);  in fsl_qspi_get_name()  local
820 	if (of_get_available_child_count(q->dev->of_node) == 1)  in fsl_qspi_get_name()
821 		return dev_name(q->dev);  in fsl_qspi_get_name()
824 			      "%s-%d", dev_name(q->dev),  in fsl_qspi_get_name()
848 	struct fsl_qspi *q;  in fsl_qspi_probe()  local
851 	ctlr = spi_alloc_host(&pdev->dev, sizeof(*q));  in fsl_qspi_probe()
858 	q = spi_controller_get_devdata(ctlr);  in fsl_qspi_probe()
859 	q->dev = dev;  in fsl_qspi_probe()
860 	q->devtype_data = of_device_get_match_data(dev);  in fsl_qspi_probe()
861 	if (!q->devtype_data) {  in fsl_qspi_probe()
866 	platform_set_drvdata(pdev, q);  in fsl_qspi_probe()
869 	q->iobase = devm_platform_ioremap_resource_byname(pdev, "QuadSPI");  in fsl_qspi_probe()
870 	if (IS_ERR(q->iobase)) {  in fsl_qspi_probe()
871 		ret = PTR_ERR(q->iobase);  in fsl_qspi_probe()
881 	q->memmap_phy = res->start;  in fsl_qspi_probe()
883 	q->ahb_addr = devm_ioremap(dev, q->memmap_phy,  in fsl_qspi_probe()
884 				   (q->devtype_data->ahb_buf_size * 4));  in fsl_qspi_probe()
885 	if (!q->ahb_addr) {  in fsl_qspi_probe()
891 	q->clk_en = devm_clk_get(dev, "qspi_en");  in fsl_qspi_probe()
892 	if (IS_ERR(q->clk_en)) {  in fsl_qspi_probe()
893 		ret = PTR_ERR(q->clk_en);  in fsl_qspi_probe()
897 	q->clk = devm_clk_get(dev, "qspi");  in fsl_qspi_probe()
898 	if (IS_ERR(q->clk)) {  in fsl_qspi_probe()
899 		ret = PTR_ERR(q->clk);  in fsl_qspi_probe()
903 	ret = fsl_qspi_clk_prep_enable(q);  in fsl_qspi_probe()
915 			fsl_qspi_irq_handler, 0, pdev->name, q);  in fsl_qspi_probe()
921 	mutex_init(&q->lock);  in fsl_qspi_probe()
927 	fsl_qspi_default_setup(q);  in fsl_qspi_probe()
938 	mutex_destroy(&q->lock);  in fsl_qspi_probe()
941 	fsl_qspi_clk_disable_unprep(q);  in fsl_qspi_probe()
952 	struct fsl_qspi *q = platform_get_drvdata(pdev);  in fsl_qspi_remove()  local
955 	qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);  in fsl_qspi_remove()
956 	qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);  in fsl_qspi_remove()
958 	fsl_qspi_clk_disable_unprep(q);  in fsl_qspi_remove()
960 	mutex_destroy(&q->lock);  in fsl_qspi_remove()
970 	struct fsl_qspi *q = dev_get_drvdata(dev);  in fsl_qspi_resume()  local
972 	fsl_qspi_default_setup(q);  in fsl_qspi_resume()