81 	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;  in dw_spi_mscc_set_cs()  local
90 		writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);  in dw_spi_mscc_set_cs()
100 	struct dw_spi_mscc *dwsmscc;  in dw_spi_mscc_init()  local
102 	dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);  in dw_spi_mscc_init()
103 	if (!dwsmscc)  in dw_spi_mscc_init()
106 	dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1);  in dw_spi_mscc_init()
107 	if (IS_ERR(dwsmscc->spi_mst)) {  in dw_spi_mscc_init()
109 		return PTR_ERR(dwsmscc->spi_mst);  in dw_spi_mscc_init()
112 	dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);  in dw_spi_mscc_init()
113 	if (IS_ERR(dwsmscc->syscon))  in dw_spi_mscc_init()
114 		return PTR_ERR(dwsmscc->syscon);  in dw_spi_mscc_init()
117 	writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);  in dw_spi_mscc_init()
120 	regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,  in dw_spi_mscc_init()
125 	dwsmmio->priv = dwsmscc;  in dw_spi_mscc_init()
154 	struct dw_spi_mscc *dwsmscc = dwsmmio->priv;  in dw_spi_sparx5_set_cs()  local
159 		regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 1);  in dw_spi_sparx5_set_cs()
161 		regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~BIT(cs));  in dw_spi_sparx5_set_cs()
166 		regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~0);  in dw_spi_sparx5_set_cs()
170 		regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 0);  in dw_spi_sparx5_set_cs()
181 	struct dw_spi_mscc *dwsmscc;  in dw_spi_mscc_sparx5_init()  local
188 	dwsmscc = devm_kzalloc(dev, sizeof(*dwsmscc), GFP_KERNEL);  in dw_spi_mscc_sparx5_init()
189 	if (!dwsmscc)  in dw_spi_mscc_sparx5_init()
192 	dwsmscc->syscon =  in dw_spi_mscc_sparx5_init()
194 	if (IS_ERR(dwsmscc->syscon)) {  in dw_spi_mscc_sparx5_init()
196 		return PTR_ERR(dwsmscc->syscon);  in dw_spi_mscc_sparx5_init()
200 	dwsmmio->priv = dwsmscc;  in dw_spi_mscc_sparx5_init()