Lines Matching +full:spi +full:- +full:cs +full:- +full:setup +full:- +full:delay +full:- +full:ns
1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
29 #include <linux/spi/spi.h>
30 #include <linux/spi/spi-mem.h>
33 #define CQSPI_NAME "cadence-qspi"
65 u8 cs; member
304 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_is_idle()
311 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); in cqspi_get_rd_sram_level()
321 dma_status = readl(cqspi->iobase + in cqspi_get_versal_dma_status()
323 writel(dma_status, cqspi->iobase + in cqspi_get_versal_dma_status()
333 struct device *device = &cqspi->pdev->dev; in cqspi_irq_handler()
339 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); in cqspi_irq_handler()
342 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); in cqspi_irq_handler()
344 if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { in cqspi_irq_handler()
345 if (ddata->get_dma_status(cqspi)) { in cqspi_irq_handler()
346 complete(&cqspi->transfer_complete); in cqspi_irq_handler()
351 else if (!cqspi->slow_sram) in cqspi_irq_handler()
357 complete(&cqspi->transfer_complete); in cqspi_irq_handler()
366 rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; in cqspi_calc_rdreg()
367 rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; in cqspi_calc_rdreg()
368 rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; in cqspi_calc_rdreg()
377 if (!op->dummy.nbytes) in cqspi_calc_dummy()
380 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); in cqspi_calc_dummy()
381 if (op->cmd.dtr) in cqspi_calc_dummy()
410 dev_err(&cqspi->pdev->dev, in cqspi_wait_idle()
413 return -ETIMEDOUT; in cqspi_wait_idle()
422 void __iomem *reg_base = cqspi->iobase; in cqspi_exec_flash_cmd()
435 dev_err(&cqspi->pdev->dev, in cqspi_exec_flash_cmd()
448 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_setup_opcode_ext()
449 void __iomem *reg_base = cqspi->iobase; in cqspi_setup_opcode_ext()
453 if (op->cmd.nbytes != 2) in cqspi_setup_opcode_ext()
454 return -EINVAL; in cqspi_setup_opcode_ext()
457 ext = op->cmd.opcode & 0xff; in cqspi_setup_opcode_ext()
470 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_enable_dtr()
471 void __iomem *reg_base = cqspi->iobase; in cqspi_enable_dtr()
481 if (op->cmd.dtr) { in cqspi_enable_dtr()
502 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_command_read()
503 void __iomem *reg_base = cqspi->iobase; in cqspi_command_read()
504 u8 *rxbuf = op->data.buf.in; in cqspi_command_read()
506 size_t n_rx = op->data.nbytes; in cqspi_command_read()
518 dev_err(&cqspi->pdev->dev, in cqspi_command_read()
521 return -EINVAL; in cqspi_command_read()
524 if (op->cmd.dtr) in cqspi_command_read()
525 opcode = op->cmd.opcode >> 8; in cqspi_command_read()
527 opcode = op->cmd.opcode; in cqspi_command_read()
536 return -EOPNOTSUPP; in cqspi_command_read()
545 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) in cqspi_command_read()
548 /* setup ADDR BIT field */ in cqspi_command_read()
549 if (op->addr.nbytes) { in cqspi_command_read()
551 reg |= ((op->addr.nbytes - 1) & in cqspi_command_read()
555 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); in cqspi_command_read()
572 read_len = n_rx - read_len; in cqspi_command_read()
585 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_command_write()
586 void __iomem *reg_base = cqspi->iobase; in cqspi_command_write()
588 const u8 *txbuf = op->data.buf.out; in cqspi_command_write()
589 size_t n_tx = op->data.nbytes; in cqspi_command_write()
600 dev_err(&cqspi->pdev->dev, in cqspi_command_write()
603 return -EINVAL; in cqspi_command_write()
609 if (op->cmd.dtr) in cqspi_command_write()
610 opcode = op->cmd.opcode >> 8; in cqspi_command_write()
612 opcode = op->cmd.opcode; in cqspi_command_write()
616 if (op->addr.nbytes) { in cqspi_command_write()
618 reg |= ((op->addr.nbytes - 1) & in cqspi_command_write()
622 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); in cqspi_command_write()
627 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) in cqspi_command_write()
637 write_len = n_tx - 4; in cqspi_command_write()
654 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_read_setup()
655 void __iomem *reg_base = cqspi->iobase; in cqspi_read_setup()
665 if (op->cmd.dtr) in cqspi_read_setup()
666 opcode = op->cmd.opcode >> 8; in cqspi_read_setup()
668 opcode = op->cmd.opcode; in cqspi_read_setup()
673 /* Setup dummy clock cycles */ in cqspi_read_setup()
677 return -EOPNOTSUPP; in cqspi_read_setup()
688 reg |= (op->addr.nbytes - 1); in cqspi_read_setup()
697 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_indirect_read_execute()
698 struct device *dev = &cqspi->pdev->dev; in cqspi_indirect_read_execute()
699 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_read_execute()
700 void __iomem *ahb_base = cqspi->ahb_base; in cqspi_indirect_read_execute()
721 if (!cqspi->slow_sram) in cqspi_indirect_read_execute()
726 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_read_execute()
731 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_indirect_read_execute()
733 ret = -ETIMEDOUT; in cqspi_indirect_read_execute()
739 if (cqspi->slow_sram) in cqspi_indirect_read_execute()
752 bytes_to_read *= cqspi->fifo_width; in cqspi_indirect_read_execute()
765 (rxbuf_end - rxbuf), in cqspi_indirect_read_execute()
769 remaining -= bytes_to_read; in cqspi_indirect_read_execute()
774 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_read_execute()
775 if (cqspi->slow_sram) in cqspi_indirect_read_execute()
808 void __iomem *reg_base = cqspi->iobase; in cqspi_controller_enable()
825 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_versal_indirect_read_dma()
826 struct device *dev = &cqspi->pdev->dev; in cqspi_versal_indirect_read_dma()
827 void __iomem *reg_base = cqspi->iobase; in cqspi_versal_indirect_read_dma()
836 bytes_to_dma = (n_rx - bytes_rem); in cqspi_versal_indirect_read_dma()
841 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); in cqspi_versal_indirect_read_dma()
847 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
849 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
856 return -ENOMEM; in cqspi_versal_indirect_read_dma()
881 writel(cqspi->trigger_address, reg_base + in cqspi_versal_indirect_read_dma()
894 reinit_completion(&cqspi->transfer_complete); in cqspi_versal_indirect_read_dma()
896 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_versal_indirect_read_dma()
898 ret = -ETIMEDOUT; in cqspi_versal_indirect_read_dma()
903 writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); in cqspi_versal_indirect_read_dma()
907 cqspi->iobase + CQSPI_REG_INDIRECTRD); in cqspi_versal_indirect_read_dma()
912 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
914 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
918 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, in cqspi_versal_indirect_read_dma()
945 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
947 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
949 zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); in cqspi_versal_indirect_read_dma()
959 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_write_setup()
960 void __iomem *reg_base = cqspi->iobase; in cqspi_write_setup()
967 if (op->cmd.dtr) in cqspi_write_setup()
968 opcode = op->cmd.opcode >> 8; in cqspi_write_setup()
970 opcode = op->cmd.opcode; in cqspi_write_setup()
974 reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; in cqspi_write_setup()
975 reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; in cqspi_write_setup()
981 * SPI NAND flashes require the address of the status register to be in cqspi_write_setup()
982 * passed in the Read SR command. Also, some SPI NOR flashes like the in cqspi_write_setup()
983 * cypress Semper flash expect a 4-byte dummy address in the Read SR in cqspi_write_setup()
987 * command when doing auto-HW polling. So, disable write completion in cqspi_write_setup()
988 * polling on the controller's side. spinand and spi-nor will take in cqspi_write_setup()
991 if (cqspi->wr_completion) { in cqspi_write_setup()
997 * for write completion in case of bubble in SPI transaction in cqspi_write_setup()
1000 cqspi->use_direct_mode_wr = false; in cqspi_write_setup()
1005 reg |= (op->addr.nbytes - 1); in cqspi_write_setup()
1014 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_indirect_write_execute()
1015 struct device *dev = &cqspi->pdev->dev; in cqspi_indirect_write_execute()
1016 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_write_execute()
1029 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_write_execute()
1035 * QSPI_REF_CLK delay is required for the above bit to in cqspi_indirect_write_execute()
1037 * cycles of delay. in cqspi_indirect_write_execute()
1039 if (cqspi->wr_delay) in cqspi_indirect_write_execute()
1040 ndelay(cqspi->wr_delay); in cqspi_indirect_write_execute()
1046 if (cqspi->apb_ahb_hazard) in cqspi_indirect_write_execute()
1057 iowrite32_rep(cqspi->ahb_base, txbuf, write_words); in cqspi_indirect_write_execute()
1064 iowrite32(temp, cqspi->ahb_base); in cqspi_indirect_write_execute()
1068 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_indirect_write_execute()
1071 ret = -ETIMEDOUT; in cqspi_indirect_write_execute()
1075 remaining -= write_bytes; in cqspi_indirect_write_execute()
1078 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_write_execute()
1111 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_chipselect()
1112 void __iomem *reg_base = cqspi->iobase; in cqspi_chipselect()
1113 unsigned int chip_select = f_pdata->cs; in cqspi_chipselect()
1117 if (cqspi->is_decoded_cs) { in cqspi_chipselect()
1122 /* Convert CS if without decoder. in cqspi_chipselect()
1151 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_delay()
1152 void __iomem *iobase = cqspi->iobase; in cqspi_delay()
1153 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; in cqspi_delay()
1159 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); in cqspi_delay()
1161 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); in cqspi_delay()
1166 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); in cqspi_delay()
1167 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); in cqspi_delay()
1168 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); in cqspi_delay()
1183 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; in cqspi_config_baudrate_div()
1184 void __iomem *reg_base = cqspi->iobase; in cqspi_config_baudrate_div()
1188 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; in cqspi_config_baudrate_div()
1193 dev_warn(&cqspi->pdev->dev, in cqspi_config_baudrate_div()
1195 cqspi->sclk, ref_clk_hz/((div+1)*2)); in cqspi_config_baudrate_div()
1206 const unsigned int delay) in cqspi_readdata_capture() argument
1208 void __iomem *reg_base = cqspi->iobase; in cqspi_readdata_capture()
1221 reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) in cqspi_readdata_capture()
1230 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_configure()
1231 int switch_cs = (cqspi->current_cs != f_pdata->cs); in cqspi_configure()
1232 int switch_ck = (cqspi->sclk != sclk); in cqspi_configure()
1239 cqspi->current_cs = f_pdata->cs; in cqspi_configure()
1243 /* Setup baudrate divisor and delays */ in cqspi_configure()
1245 cqspi->sclk = sclk; in cqspi_configure()
1248 cqspi_readdata_capture(cqspi, !cqspi->rclk_en, in cqspi_configure()
1249 f_pdata->read_delay); in cqspi_configure()
1259 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_write()
1260 loff_t to = op->addr.val; in cqspi_write()
1261 size_t len = op->data.nbytes; in cqspi_write()
1262 const u_char *buf = op->data.buf.out; in cqspi_write()
1270 * Some flashes like the Cypress Semper flash expect a dummy 4-byte in cqspi_write()
1277 if (!op->cmd.dtr && cqspi->use_direct_mode && in cqspi_write()
1278 cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) { in cqspi_write()
1279 memcpy_toio(cqspi->ahb_base + to, buf, len); in cqspi_write()
1290 complete(&cqspi->rx_dma_complete); in cqspi_rx_dma_callback()
1296 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_direct_read_execute()
1297 struct device *dev = &cqspi->pdev->dev; in cqspi_direct_read_execute()
1299 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; in cqspi_direct_read_execute()
1306 if (!cqspi->rx_chan || !virt_addr_valid(buf)) { in cqspi_direct_read_execute()
1307 memcpy_fromio(buf, cqspi->ahb_base + from, len); in cqspi_direct_read_execute()
1311 ddev = cqspi->rx_chan->device->dev; in cqspi_direct_read_execute()
1315 return -ENOMEM; in cqspi_direct_read_execute()
1317 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, in cqspi_direct_read_execute()
1321 ret = -EIO; in cqspi_direct_read_execute()
1325 tx->callback = cqspi_rx_dma_callback; in cqspi_direct_read_execute()
1326 tx->callback_param = cqspi; in cqspi_direct_read_execute()
1327 cookie = tx->tx_submit(tx); in cqspi_direct_read_execute()
1328 reinit_completion(&cqspi->rx_dma_complete); in cqspi_direct_read_execute()
1333 ret = -EIO; in cqspi_direct_read_execute()
1337 dma_async_issue_pending(cqspi->rx_chan); in cqspi_direct_read_execute()
1338 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, in cqspi_direct_read_execute()
1340 dmaengine_terminate_sync(cqspi->rx_chan); in cqspi_direct_read_execute()
1342 ret = -ETIMEDOUT; in cqspi_direct_read_execute()
1355 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_read()
1356 struct device *dev = &cqspi->pdev->dev; in cqspi_read()
1358 loff_t from = op->addr.val; in cqspi_read()
1359 size_t len = op->data.nbytes; in cqspi_read()
1360 u_char *buf = op->data.buf.in; in cqspi_read()
1370 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) in cqspi_read()
1373 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && in cqspi_read()
1375 return ddata->indirect_read_dma(f_pdata, buf, from, len); in cqspi_read()
1382 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); in cqspi_mem_process()
1385 f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)]; in cqspi_mem_process()
1386 cqspi_configure(f_pdata, mem->spi->max_speed_hz); in cqspi_mem_process()
1388 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { in cqspi_mem_process()
1394 if (!op->addr.nbytes || in cqspi_mem_process()
1395 op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) in cqspi_mem_process()
1401 if (!op->addr.nbytes || !op->data.buf.out) in cqspi_mem_process()
1413 dev_err(&mem->spi->dev, "operation failed with %d\n", ret); in cqspi_exec_mem_op()
1424 * op->dummy.dtr is required for converting nbytes into ncycles. in cqspi_supports_mem_op()
1427 all_true = op->cmd.dtr && in cqspi_supports_mem_op()
1428 (!op->addr.nbytes || op->addr.dtr) && in cqspi_supports_mem_op()
1429 (!op->dummy.nbytes || op->dummy.dtr) && in cqspi_supports_mem_op()
1430 (!op->data.nbytes || op->data.dtr); in cqspi_supports_mem_op()
1432 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && in cqspi_supports_mem_op()
1433 !op->data.dtr; in cqspi_supports_mem_op()
1436 /* Right now we only support 8-8-8 DTR mode. */ in cqspi_supports_mem_op()
1437 if (op->cmd.nbytes && op->cmd.buswidth != 8) in cqspi_supports_mem_op()
1439 if (op->addr.nbytes && op->addr.buswidth != 8) in cqspi_supports_mem_op()
1441 if (op->data.nbytes && op->data.buswidth != 8) in cqspi_supports_mem_op()
1455 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { in cqspi_of_get_flash_pdata()
1456 dev_err(&pdev->dev, "couldn't determine read-delay\n"); in cqspi_of_get_flash_pdata()
1457 return -ENXIO; in cqspi_of_get_flash_pdata()
1460 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { in cqspi_of_get_flash_pdata()
1461 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); in cqspi_of_get_flash_pdata()
1462 return -ENXIO; in cqspi_of_get_flash_pdata()
1465 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { in cqspi_of_get_flash_pdata()
1466 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); in cqspi_of_get_flash_pdata()
1467 return -ENXIO; in cqspi_of_get_flash_pdata()
1470 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { in cqspi_of_get_flash_pdata()
1471 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); in cqspi_of_get_flash_pdata()
1472 return -ENXIO; in cqspi_of_get_flash_pdata()
1475 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { in cqspi_of_get_flash_pdata()
1476 dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); in cqspi_of_get_flash_pdata()
1477 return -ENXIO; in cqspi_of_get_flash_pdata()
1480 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { in cqspi_of_get_flash_pdata()
1481 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); in cqspi_of_get_flash_pdata()
1482 return -ENXIO; in cqspi_of_get_flash_pdata()
1490 struct device *dev = &cqspi->pdev->dev; in cqspi_of_get_pdata()
1491 struct device_node *np = dev->of_node; in cqspi_of_get_pdata()
1494 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); in cqspi_of_get_pdata()
1496 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { in cqspi_of_get_pdata()
1497 dev_err(dev, "couldn't determine fifo-depth\n"); in cqspi_of_get_pdata()
1498 return -ENXIO; in cqspi_of_get_pdata()
1501 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { in cqspi_of_get_pdata()
1502 dev_err(dev, "couldn't determine fifo-width\n"); in cqspi_of_get_pdata()
1503 return -ENXIO; in cqspi_of_get_pdata()
1506 if (of_property_read_u32(np, "cdns,trigger-address", in cqspi_of_get_pdata()
1507 &cqspi->trigger_address)) { in cqspi_of_get_pdata()
1508 dev_err(dev, "couldn't determine trigger-address\n"); in cqspi_of_get_pdata()
1509 return -ENXIO; in cqspi_of_get_pdata()
1512 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) in cqspi_of_get_pdata()
1513 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; in cqspi_of_get_pdata()
1515 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); in cqspi_of_get_pdata()
1517 if (!of_property_read_u32_array(np, "power-domains", id, in cqspi_of_get_pdata()
1519 cqspi->pd_dev_id = id[1]; in cqspi_of_get_pdata()
1531 writel(0, cqspi->iobase + CQSPI_REG_REMAP); in cqspi_controller_init()
1534 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); in cqspi_controller_init()
1537 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); in cqspi_controller_init()
1540 writel(cqspi->trigger_address, in cqspi_controller_init()
1541 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); in cqspi_controller_init()
1543 /* Program read watermark -- 1/2 of the FIFO. */ in cqspi_controller_init()
1544 writel(cqspi->fifo_depth * cqspi->fifo_width / 2, in cqspi_controller_init()
1545 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); in cqspi_controller_init()
1546 /* Program write watermark -- 1/8 of the FIFO. */ in cqspi_controller_init()
1547 writel(cqspi->fifo_depth * cqspi->fifo_width / 8, in cqspi_controller_init()
1548 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); in cqspi_controller_init()
1551 if (!cqspi->use_direct_mode) { in cqspi_controller_init()
1552 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1554 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1558 if (cqspi->use_dma_read) { in cqspi_controller_init()
1559 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1561 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1574 cqspi->rx_chan = dma_request_chan_by_mask(&mask); in cqspi_request_mmap_dma()
1575 if (IS_ERR(cqspi->rx_chan)) { in cqspi_request_mmap_dma()
1576 int ret = PTR_ERR(cqspi->rx_chan); in cqspi_request_mmap_dma()
1578 cqspi->rx_chan = NULL; in cqspi_request_mmap_dma()
1579 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); in cqspi_request_mmap_dma()
1581 init_completion(&cqspi->rx_dma_complete); in cqspi_request_mmap_dma()
1588 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller); in cqspi_get_name()
1589 struct device *dev = &cqspi->pdev->dev; in cqspi_get_name()
1592 spi_get_chipselect(mem->spi, 0)); in cqspi_get_name()
1607 struct platform_device *pdev = cqspi->pdev; in cqspi_setup_flash()
1608 struct device *dev = &pdev->dev; in cqspi_setup_flash()
1609 struct device_node *np = dev->of_node; in cqspi_setup_flash()
1611 unsigned int cs; in cqspi_setup_flash() local
1615 for_each_available_child_of_node(dev->of_node, np) { in cqspi_setup_flash()
1616 ret = of_property_read_u32(np, "reg", &cs); in cqspi_setup_flash()
1623 if (cs >= CQSPI_MAX_CHIPSELECT) { in cqspi_setup_flash()
1624 dev_err(dev, "Chip select %d out of range.\n", cs); in cqspi_setup_flash()
1626 return -EINVAL; in cqspi_setup_flash()
1629 f_pdata = &cqspi->f_pdata[cs]; in cqspi_setup_flash()
1630 f_pdata->cqspi = cqspi; in cqspi_setup_flash()
1631 f_pdata->cs = cs; in cqspi_setup_flash()
1652 ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk); in cqspi_jh7110_clk_init()
1654 dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__); in cqspi_jh7110_clk_init()
1658 cqspi->clks[CLK_QSPI_APB] = qspiclk[0].clk; in cqspi_jh7110_clk_init()
1659 cqspi->clks[CLK_QSPI_AHB] = qspiclk[1].clk; in cqspi_jh7110_clk_init()
1661 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]); in cqspi_jh7110_clk_init()
1663 dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__); in cqspi_jh7110_clk_init()
1667 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]); in cqspi_jh7110_clk_init()
1669 dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__); in cqspi_jh7110_clk_init()
1673 cqspi->is_jh7110 = true; in cqspi_jh7110_clk_init()
1678 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); in cqspi_jh7110_clk_init()
1685 clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]); in cqspi_jh7110_disable_clk()
1686 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); in cqspi_jh7110_disable_clk()
1692 struct device *dev = &pdev->dev; in cqspi_probe()
1699 host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi)); in cqspi_probe()
1701 dev_err(&pdev->dev, "devm_spi_alloc_host failed\n"); in cqspi_probe()
1702 return -ENOMEM; in cqspi_probe()
1704 host->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; in cqspi_probe()
1705 host->mem_ops = &cqspi_mem_ops; in cqspi_probe()
1706 host->mem_caps = &cqspi_mem_caps; in cqspi_probe()
1707 host->dev.of_node = pdev->dev.of_node; in cqspi_probe()
1711 cqspi->pdev = pdev; in cqspi_probe()
1712 cqspi->host = host; in cqspi_probe()
1713 cqspi->is_jh7110 = false; in cqspi_probe()
1720 return -ENODEV; in cqspi_probe()
1724 cqspi->clk = devm_clk_get(dev, NULL); in cqspi_probe()
1725 if (IS_ERR(cqspi->clk)) { in cqspi_probe()
1727 ret = PTR_ERR(cqspi->clk); in cqspi_probe()
1732 cqspi->iobase = devm_platform_ioremap_resource(pdev, 0); in cqspi_probe()
1733 if (IS_ERR(cqspi->iobase)) { in cqspi_probe()
1735 ret = PTR_ERR(cqspi->iobase); in cqspi_probe()
1740 cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb); in cqspi_probe()
1741 if (IS_ERR(cqspi->ahb_base)) { in cqspi_probe()
1743 ret = PTR_ERR(cqspi->ahb_base); in cqspi_probe()
1746 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; in cqspi_probe()
1747 cqspi->ahb_size = resource_size(res_ahb); in cqspi_probe()
1749 init_completion(&cqspi->transfer_complete); in cqspi_probe()
1754 return -ENXIO; in cqspi_probe()
1761 ret = clk_prepare_enable(cqspi->clk); in cqspi_probe()
1775 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); in cqspi_probe()
1782 if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { in cqspi_probe()
1799 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); in cqspi_probe()
1800 host->max_speed_hz = cqspi->master_ref_clk_hz; in cqspi_probe()
1803 cqspi->wr_completion = true; in cqspi_probe()
1807 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) in cqspi_probe()
1808 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, in cqspi_probe()
1809 cqspi->master_ref_clk_hz); in cqspi_probe()
1810 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) in cqspi_probe()
1811 host->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; in cqspi_probe()
1812 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) { in cqspi_probe()
1813 cqspi->use_direct_mode = true; in cqspi_probe()
1814 cqspi->use_direct_mode_wr = true; in cqspi_probe()
1816 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) in cqspi_probe()
1817 cqspi->use_dma_read = true; in cqspi_probe()
1818 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) in cqspi_probe()
1819 cqspi->wr_completion = false; in cqspi_probe()
1820 if (ddata->quirks & CQSPI_SLOW_SRAM) in cqspi_probe()
1821 cqspi->slow_sram = true; in cqspi_probe()
1822 if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) in cqspi_probe()
1823 cqspi->apb_ahb_hazard = true; in cqspi_probe()
1825 if (ddata->jh7110_clk_init) { in cqspi_probe()
1831 if (of_device_is_compatible(pdev->dev.of_node, in cqspi_probe()
1832 "xlnx,versal-ospi-1.0")) { in cqspi_probe()
1833 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); in cqspi_probe()
1840 pdev->name, cqspi); in cqspi_probe()
1848 cqspi->current_cs = -1; in cqspi_probe()
1849 cqspi->sclk = 0; in cqspi_probe()
1851 host->num_chipselect = cqspi->num_chipselect; in cqspi_probe()
1855 dev_err(dev, "failed to setup flash parameters %d\n", ret); in cqspi_probe()
1859 if (cqspi->use_direct_mode) { in cqspi_probe()
1861 if (ret == -EPROBE_DEFER) in cqspi_probe()
1867 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); in cqspi_probe()
1875 if (cqspi->is_jh7110) in cqspi_probe()
1877 clk_disable_unprepare(cqspi->clk); in cqspi_probe()
1889 spi_unregister_controller(cqspi->host); in cqspi_remove()
1892 if (cqspi->rx_chan) in cqspi_remove()
1893 dma_release_channel(cqspi->rx_chan); in cqspi_remove()
1895 clk_disable_unprepare(cqspi->clk); in cqspi_remove()
1897 if (cqspi->is_jh7110) in cqspi_remove()
1900 pm_runtime_put_sync(&pdev->dev); in cqspi_remove()
1901 pm_runtime_disable(&pdev->dev); in cqspi_remove()
1909 ret = spi_controller_suspend(cqspi->host); in cqspi_suspend()
1912 clk_disable_unprepare(cqspi->clk); in cqspi_suspend()
1921 clk_prepare_enable(cqspi->clk); in cqspi_resume()
1925 cqspi->current_cs = -1; in cqspi_resume()
1926 cqspi->sclk = 0; in cqspi_resume()
1928 return spi_controller_resume(cqspi->host); in cqspi_resume()
1974 .compatible = "cdns,qspi-nor",
1978 .compatible = "ti,k2g-qspi",
1982 .compatible = "ti,am654-ospi",
1986 .compatible = "intel,lgm-qspi",
1990 .compatible = "xlnx,versal-ospi-1.0",
1994 .compatible = "intel,socfpga-qspi",
1998 .compatible = "starfive,jh7110-qspi",
2002 .compatible = "amd,pensando-elba-qspi",