422 	void __iomem *reg_base = cqspi->iobase;  in cqspi_exec_flash_cmd()  local
426 	writel(reg, reg_base + CQSPI_REG_CMDCTRL);  in cqspi_exec_flash_cmd()
429 	writel(reg, reg_base + CQSPI_REG_CMDCTRL);  in cqspi_exec_flash_cmd()
432 	ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,  in cqspi_exec_flash_cmd()
449 	void __iomem *reg_base = cqspi->iobase;  in cqspi_setup_opcode_ext()  local
459 	reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER);  in cqspi_setup_opcode_ext()
462 	writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER);  in cqspi_setup_opcode_ext()
471 	void __iomem *reg_base = cqspi->iobase;  in cqspi_enable_dtr()  local
475 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cqspi_enable_dtr()
494 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cqspi_enable_dtr()
503 	void __iomem *reg_base = cqspi->iobase;  in cqspi_command_read()  local
532 	writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);  in cqspi_command_read()
555 		writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);  in cqspi_command_read()
562 	reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);  in cqspi_command_read()
570 		reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);  in cqspi_command_read()
577 	writel(0, reg_base + CQSPI_REG_CMDCTRL);  in cqspi_command_read()
586 	void __iomem *reg_base = cqspi->iobase;  in cqspi_command_write()  local
607 	writel(reg, reg_base + CQSPI_REG_RD_INSTR);  in cqspi_command_write()
622 		writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);  in cqspi_command_write()
633 		writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);  in cqspi_command_write()
639 			writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);  in cqspi_command_write()
646 	writel(0, reg_base + CQSPI_REG_CMDCTRL);  in cqspi_command_write()
655 	void __iomem *reg_base = cqspi->iobase;  in cqspi_read_setup()  local
683 	writel(reg, reg_base + CQSPI_REG_RD_INSTR);  in cqspi_read_setup()
686 	reg = readl(reg_base + CQSPI_REG_SIZE);  in cqspi_read_setup()
689 	writel(reg, reg_base + CQSPI_REG_SIZE);  in cqspi_read_setup()
699 	void __iomem *reg_base = cqspi->iobase;  in cqspi_indirect_read_execute()  local
707 	writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);  in cqspi_indirect_read_execute()
708 	writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);  in cqspi_indirect_read_execute()
711 	writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);  in cqspi_indirect_read_execute()
722 		writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_read_execute()
724 		writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_read_execute()
728 	       reg_base + CQSPI_REG_INDIRECTRD);  in cqspi_indirect_read_execute()
740 			writel(0x0, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_read_execute()
776 				writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_read_execute()
781 	ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,  in cqspi_indirect_read_execute()
789 	writel(0, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_read_execute()
792 	writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);  in cqspi_indirect_read_execute()
798 	writel(0, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_read_execute()
802 	       reg_base + CQSPI_REG_INDIRECTRD);  in cqspi_indirect_read_execute()
808 	void __iomem *reg_base = cqspi->iobase;  in cqspi_controller_enable()  local
811 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cqspi_controller_enable()
818 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cqspi_controller_enable()
827 	void __iomem *reg_base = cqspi->iobase;  in cqspi_versal_indirect_read_dma()  local
859 	writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);  in cqspi_versal_indirect_read_dma()
860 	writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES);  in cqspi_versal_indirect_read_dma()
862 	       reg_base + CQSPI_REG_INDTRIG_ADDRRANGE);  in cqspi_versal_indirect_read_dma()
865 	writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);  in cqspi_versal_indirect_read_dma()
869 	       reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN);  in cqspi_versal_indirect_read_dma()
872 	writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA);  in cqspi_versal_indirect_read_dma()
876 	       reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR);  in cqspi_versal_indirect_read_dma()
878 	       reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB);  in cqspi_versal_indirect_read_dma()
881 	writel(cqspi->trigger_address, reg_base +  in cqspi_versal_indirect_read_dma()
885 	writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE);  in cqspi_versal_indirect_read_dma()
889 	       reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL);  in cqspi_versal_indirect_read_dma()
892 	       reg_base + CQSPI_REG_INDIRECTRD);  in cqspi_versal_indirect_read_dma()
937 	writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS);  in cqspi_versal_indirect_read_dma()
941 	       reg_base + CQSPI_REG_INDIRECTRD);  in cqspi_versal_indirect_read_dma()
960 	void __iomem *reg_base = cqspi->iobase;  in cqspi_write_setup()  local
976 	writel(reg, reg_base + CQSPI_REG_WR_INSTR);  in cqspi_write_setup()
978 	writel(reg, reg_base + CQSPI_REG_RD_INSTR);  in cqspi_write_setup()
992 		reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);  in cqspi_write_setup()
994 		writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);  in cqspi_write_setup()
1003 	reg = readl(reg_base + CQSPI_REG_SIZE);  in cqspi_write_setup()
1006 	writel(reg, reg_base + CQSPI_REG_SIZE);  in cqspi_write_setup()
1016 	void __iomem *reg_base = cqspi->iobase;  in cqspi_indirect_write_execute()  local
1021 	writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);  in cqspi_indirect_write_execute()
1022 	writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);  in cqspi_indirect_write_execute()
1025 	writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);  in cqspi_indirect_write_execute()
1027 	writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_write_execute()
1031 	       reg_base + CQSPI_REG_INDIRECTWR);  in cqspi_indirect_write_execute()
1047 		readl(reg_base + CQSPI_REG_INDIRECTWR);  in cqspi_indirect_write_execute()
1082 	ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,  in cqspi_indirect_write_execute()
1090 	writel(0, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_write_execute()
1093 	writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);  in cqspi_indirect_write_execute()
1101 	writel(0, reg_base + CQSPI_REG_IRQMASK);  in cqspi_indirect_write_execute()
1105 	       reg_base + CQSPI_REG_INDIRECTWR);  in cqspi_indirect_write_execute()
1112 	void __iomem *reg_base = cqspi->iobase;  in cqspi_chipselect()  local
1116 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cqspi_chipselect()
1135 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cqspi_chipselect()
1184 	void __iomem *reg_base = cqspi->iobase;  in cqspi_config_baudrate_div()  local
1198 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cqspi_config_baudrate_div()
1201 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cqspi_config_baudrate_div()
1208 	void __iomem *reg_base = cqspi->iobase;  in cqspi_readdata_capture()  local
1211 	reg = readl(reg_base + CQSPI_REG_READCAPTURE);  in cqspi_readdata_capture()
1224 	writel(reg, reg_base + CQSPI_REG_READCAPTURE);  in cqspi_readdata_capture()