121 static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data)  in spireg_write()  function
132 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_auto_cs_unset()
141 	spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);  in a3700_spi_activate_cs()
151 	spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);  in a3700_spi_deactivate_cs()
180 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_pin_mode_set()
194 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_fifo_mode_set()
214 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_mode_set()
236 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_clock_set()
241 		spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val);  in a3700_spi_clock_set()
254 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_bytelen_set()
266 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_fifo_flush()
287 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_init()
293 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_init()
307 	spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);  in a3700_spi_init()
308 	spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0);  in a3700_spi_init()
311 	spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);  in a3700_spi_init()
312 	spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U);  in a3700_spi_init()
330 	spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);  in a3700_spi_interrupt()
331 	spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause);  in a3700_spi_interrupt()
360 	spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG,  in a3700_spi_wait_completion()
384 	spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);  in a3700_spi_wait_completion()
411 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_fifo_thres_set()
450 	spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0);  in a3700_spi_header_set()
451 	spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0);  in a3700_spi_header_set()
452 	spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0);  in a3700_spi_header_set()
453 	spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);  in a3700_spi_header_set()
469 			spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val);  in a3700_spi_header_set()
480 			spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val);  in a3700_spi_header_set()
499 		spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, cpu_to_le32(val));  in a3700_spi_fifo_write()
552 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_transfer_abort_fifo()
564 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_transfer_abort_fifo()
623 		spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0);  in a3700_spi_transfer_one_fifo()
626 		spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG,  in a3700_spi_transfer_one_fifo()
632 		spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_transfer_one_fifo()
637 		spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_transfer_one_fifo()
711 		spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_transfer_one_fifo()
728 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_transfer_one_fifo()
762 		spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);  in a3700_spi_transfer_one_full_duplex()