Lines Matching refs:a3700_spi
101 struct a3700_spi { struct
116 static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset) in spireg_read() argument
118 return readl(a3700_spi->base + offset); in spireg_read()
121 static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data) in spireg_write() argument
123 writel(data, a3700_spi->base + offset); in spireg_write()
126 static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi) in a3700_spi_auto_cs_unset() argument
130 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_auto_cs_unset()
132 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_auto_cs_unset()
135 static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs) in a3700_spi_activate_cs() argument
139 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_spi_activate_cs()
141 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); in a3700_spi_activate_cs()
144 static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi, in a3700_spi_deactivate_cs() argument
149 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_spi_deactivate_cs()
151 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); in a3700_spi_deactivate_cs()
154 static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi, in a3700_spi_pin_mode_set() argument
159 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_pin_mode_set()
176 dev_err(&a3700_spi->host->dev, "wrong pin mode %u", pin_mode); in a3700_spi_pin_mode_set()
180 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_pin_mode_set()
185 static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi, bool enable) in a3700_spi_fifo_mode_set() argument
189 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_fifo_mode_set()
194 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_fifo_mode_set()
197 static void a3700_spi_mode_set(struct a3700_spi *a3700_spi, in a3700_spi_mode_set() argument
202 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_mode_set()
214 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_mode_set()
217 static void a3700_spi_clock_set(struct a3700_spi *a3700_spi, in a3700_spi_clock_set() argument
223 prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz); in a3700_spi_clock_set()
232 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_clock_set()
236 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_clock_set()
239 val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG); in a3700_spi_clock_set()
241 spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val); in a3700_spi_clock_set()
245 static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len) in a3700_spi_bytelen_set() argument
249 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_bytelen_set()
254 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_bytelen_set()
256 a3700_spi->byte_len = len; in a3700_spi_bytelen_set()
259 static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi) in a3700_spi_fifo_flush() argument
264 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_fifo_flush()
266 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_fifo_flush()
269 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_fifo_flush()
278 static void a3700_spi_init(struct a3700_spi *a3700_spi) in a3700_spi_init() argument
280 struct spi_controller *host = a3700_spi->host; in a3700_spi_init()
285 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_init()
287 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_init()
291 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_init()
293 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_init()
296 a3700_spi_auto_cs_unset(a3700_spi); in a3700_spi_init()
298 a3700_spi_deactivate_cs(a3700_spi, i); in a3700_spi_init()
301 a3700_spi_fifo_mode_set(a3700_spi, true); in a3700_spi_init()
304 a3700_spi_mode_set(a3700_spi, host->mode_bits); in a3700_spi_init()
307 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); in a3700_spi_init()
308 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0); in a3700_spi_init()
311 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); in a3700_spi_init()
312 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U); in a3700_spi_init()
318 struct a3700_spi *a3700_spi; in a3700_spi_interrupt() local
321 a3700_spi = spi_controller_get_devdata(host); in a3700_spi_interrupt()
324 cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG); in a3700_spi_interrupt()
326 if (!cause || !(a3700_spi->wait_mask & cause)) in a3700_spi_interrupt()
330 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); in a3700_spi_interrupt()
331 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause); in a3700_spi_interrupt()
334 complete(&a3700_spi->done); in a3700_spi_interrupt()
341 struct a3700_spi *a3700_spi; in a3700_spi_wait_completion() local
346 a3700_spi = spi_controller_get_devdata(spi->controller); in a3700_spi_wait_completion()
354 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_spi_wait_completion()
355 if (a3700_spi->wait_mask & ctrl_reg) in a3700_spi_wait_completion()
358 reinit_completion(&a3700_spi->done); in a3700_spi_wait_completion()
360 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, in a3700_spi_wait_completion()
361 a3700_spi->wait_mask); in a3700_spi_wait_completion()
364 timeout = wait_for_completion_timeout(&a3700_spi->done, in a3700_spi_wait_completion()
367 a3700_spi->wait_mask = 0; in a3700_spi_wait_completion()
380 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_spi_wait_completion()
381 if (a3700_spi->wait_mask & ctrl_reg) in a3700_spi_wait_completion()
384 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); in a3700_spi_wait_completion()
393 struct a3700_spi *a3700_spi; in a3700_spi_transfer_wait() local
395 a3700_spi = spi_controller_get_devdata(spi->controller); in a3700_spi_transfer_wait()
396 a3700_spi->wait_mask = bit_mask; in a3700_spi_transfer_wait()
401 static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi, in a3700_spi_fifo_thres_set() argument
406 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_fifo_thres_set()
411 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_fifo_thres_set()
417 struct a3700_spi *a3700_spi; in a3700_spi_transfer_setup() local
419 a3700_spi = spi_controller_get_devdata(spi->controller); in a3700_spi_transfer_setup()
421 a3700_spi_clock_set(a3700_spi, xfer->speed_hz); in a3700_spi_transfer_setup()
426 a3700_spi_bytelen_set(a3700_spi, 4); in a3700_spi_transfer_setup()
429 a3700_spi->tx_buf = xfer->tx_buf; in a3700_spi_transfer_setup()
430 a3700_spi->rx_buf = xfer->rx_buf; in a3700_spi_transfer_setup()
431 a3700_spi->buf_len = xfer->len; in a3700_spi_transfer_setup()
436 struct a3700_spi *a3700_spi = spi_controller_get_devdata(spi->controller); in a3700_spi_set_cs() local
439 a3700_spi_activate_cs(a3700_spi, spi_get_chipselect(spi, 0)); in a3700_spi_set_cs()
441 a3700_spi_deactivate_cs(a3700_spi, spi_get_chipselect(spi, 0)); in a3700_spi_set_cs()
444 static void a3700_spi_header_set(struct a3700_spi *a3700_spi) in a3700_spi_header_set() argument
450 spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0); in a3700_spi_header_set()
451 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0); in a3700_spi_header_set()
452 spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0); in a3700_spi_header_set()
453 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); in a3700_spi_header_set()
456 if (a3700_spi->tx_buf) { in a3700_spi_header_set()
465 addr_cnt = a3700_spi->buf_len % 4; in a3700_spi_header_set()
469 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val); in a3700_spi_header_set()
472 a3700_spi->buf_len -= addr_cnt; in a3700_spi_header_set()
477 val = (val << 8) | a3700_spi->tx_buf[0]; in a3700_spi_header_set()
478 a3700_spi->tx_buf++; in a3700_spi_header_set()
480 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val); in a3700_spi_header_set()
485 static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi) in a3700_is_wfifo_full() argument
489 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_is_wfifo_full()
493 static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi) in a3700_spi_fifo_write() argument
497 while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) { in a3700_spi_fifo_write()
498 val = *(u32 *)a3700_spi->tx_buf; in a3700_spi_fifo_write()
499 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, cpu_to_le32(val)); in a3700_spi_fifo_write()
500 a3700_spi->buf_len -= 4; in a3700_spi_fifo_write()
501 a3700_spi->tx_buf += 4; in a3700_spi_fifo_write()
507 static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi) in a3700_is_rfifo_empty() argument
509 u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_is_rfifo_empty()
514 static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi) in a3700_spi_fifo_read() argument
518 while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) { in a3700_spi_fifo_read()
519 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); in a3700_spi_fifo_read()
520 if (a3700_spi->buf_len >= 4) { in a3700_spi_fifo_read()
522 memcpy(a3700_spi->rx_buf, &val, 4); in a3700_spi_fifo_read()
524 a3700_spi->buf_len -= 4; in a3700_spi_fifo_read()
525 a3700_spi->rx_buf += 4; in a3700_spi_fifo_read()
532 while (a3700_spi->buf_len) { in a3700_spi_fifo_read()
533 *a3700_spi->rx_buf = val & 0xff; in a3700_spi_fifo_read()
536 a3700_spi->buf_len--; in a3700_spi_fifo_read()
537 a3700_spi->rx_buf++; in a3700_spi_fifo_read()
545 static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi) in a3700_spi_transfer_abort_fifo() argument
550 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_abort_fifo()
552 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_abort_fifo()
555 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_abort_fifo()
561 a3700_spi_fifo_flush(a3700_spi); in a3700_spi_transfer_abort_fifo()
564 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_abort_fifo()
570 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host); in a3700_spi_prepare_message() local
574 ret = clk_enable(a3700_spi->clk); in a3700_spi_prepare_message()
581 ret = a3700_spi_fifo_flush(a3700_spi); in a3700_spi_prepare_message()
585 a3700_spi_mode_set(a3700_spi, spi->mode); in a3700_spi_prepare_message()
594 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host); in a3700_spi_transfer_one_fifo() local
600 a3700_spi_fifo_mode_set(a3700_spi, true); in a3700_spi_transfer_one_fifo()
604 a3700_spi_fifo_thres_set(a3700_spi, byte_len); in a3700_spi_transfer_one_fifo()
611 a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false); in a3700_spi_transfer_one_fifo()
614 a3700_spi_fifo_flush(a3700_spi); in a3700_spi_transfer_one_fifo()
617 a3700_spi_header_set(a3700_spi); in a3700_spi_transfer_one_fifo()
623 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0); in a3700_spi_transfer_one_fifo()
626 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, in a3700_spi_transfer_one_fifo()
627 a3700_spi->buf_len); in a3700_spi_transfer_one_fifo()
629 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_one_fifo()
632 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_one_fifo()
635 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_one_fifo()
637 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_one_fifo()
645 a3700_spi->xmit_data = (a3700_spi->buf_len != 0); in a3700_spi_transfer_one_fifo()
648 while (a3700_spi->buf_len) { in a3700_spi_transfer_one_fifo()
649 if (a3700_spi->tx_buf) { in a3700_spi_transfer_one_fifo()
659 ret = a3700_spi_fifo_write(a3700_spi); in a3700_spi_transfer_one_fifo()
662 } else if (a3700_spi->rx_buf) { in a3700_spi_transfer_one_fifo()
672 ret = a3700_spi_fifo_read(a3700_spi); in a3700_spi_transfer_one_fifo()
690 if (a3700_spi->tx_buf) { in a3700_spi_transfer_one_fifo()
691 if (a3700_spi->xmit_data) { in a3700_spi_transfer_one_fifo()
709 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_one_fifo()
711 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_one_fifo()
715 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_one_fifo()
728 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_one_fifo()
732 a3700_spi_transfer_abort_fifo(a3700_spi); in a3700_spi_transfer_one_fifo()
743 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host); in a3700_spi_transfer_one_full_duplex() local
747 a3700_spi_fifo_mode_set(a3700_spi, false); in a3700_spi_transfer_one_full_duplex()
749 while (a3700_spi->buf_len) { in a3700_spi_transfer_one_full_duplex()
754 if (a3700_spi->buf_len < 4) in a3700_spi_transfer_one_full_duplex()
755 a3700_spi_bytelen_set(a3700_spi, 1); in a3700_spi_transfer_one_full_duplex()
757 if (a3700_spi->byte_len == 1) in a3700_spi_transfer_one_full_duplex()
758 val = *a3700_spi->tx_buf; in a3700_spi_transfer_one_full_duplex()
760 val = *(u32 *)a3700_spi->tx_buf; in a3700_spi_transfer_one_full_duplex()
762 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); in a3700_spi_transfer_one_full_duplex()
765 while (!(spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG) & in a3700_spi_transfer_one_full_duplex()
769 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); in a3700_spi_transfer_one_full_duplex()
771 memcpy(a3700_spi->rx_buf, &val, a3700_spi->byte_len); in a3700_spi_transfer_one_full_duplex()
773 a3700_spi->buf_len -= a3700_spi->byte_len; in a3700_spi_transfer_one_full_duplex()
774 a3700_spi->tx_buf += a3700_spi->byte_len; in a3700_spi_transfer_one_full_duplex()
775 a3700_spi->rx_buf += a3700_spi->byte_len; in a3700_spi_transfer_one_full_duplex()
799 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host); in a3700_spi_unprepare_message() local
801 clk_disable(a3700_spi->clk); in a3700_spi_unprepare_message()
818 struct a3700_spi *spi; in a3700_spi_probe()
913 struct a3700_spi *spi = spi_controller_get_devdata(host); in a3700_spi_remove()