180 	u32 max_reg;
201 	u32 intr_mask;
208 	int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
210 	u32 slave_status;
211 	u32 wr_fifo_depth;
212 	u32 rd_fifo_depth;
217 	u32 default_cols;
218 	u32 default_rows;
220 	u32 max_reg;
281 				  u32 *val)  in qcom_swrm_ahb_reg_read()
321 				  u32 *val)  in qcom_swrm_cpu_reg_read()
334 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,  in swrm_get_packed_reg_val()
337 	u32 val;  in swrm_get_packed_reg_val()
354 	u32 fifo_outstanding_data, value;  in swrm_wait_for_rd_fifo_avail()
380 	u32 fifo_outstanding_cmds, value;  in swrm_wait_for_wr_fifo_avail()
406 	u32 fifo_outstanding_cmds, value;  in swrm_wait_for_wr_fifo_done()
434 	u32 val;  in qcom_swrm_cmd_fifo_wr_cmd()
480 				     u32 len, u8 *rval)  in qcom_swrm_cmd_fifo_rd_cmd()
482 	u32 cmd_data, cmd_id, val, retry_attempt = 0;  in qcom_swrm_cmd_fifo_rd_cmd()
533 	u32 val, status;  in qcom_swrm_get_alert_slave_dev_num()
552 	u32 val;  in qcom_swrm_get_device_status()
559 		u32 s;  in qcom_swrm_get_device_status()
571 	u32 status;  in qcom_swrm_set_slave_dev_num()
591 	u32 val1, val2;  in qcom_swrm_enumerate()
668 	u32 value, intr_sts, intr_sts_masked, slave_status;  in qcom_swrm_irq_handler()
669 	u32 i;  in qcom_swrm_irq_handler()
820 	u32 val;  in qcom_swrm_init()
932 	u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);  in qcom_swrm_pre_bank_switch()
934 	u32 val;  in qcom_swrm_pre_bank_switch()
961 	u32 value;  in qcom_swrm_transport_params()
1026 	u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);  in qcom_swrm_port_enable()
1028 	u32 val;  in qcom_swrm_port_enable()
1110 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
1507 	u32 val;