Lines Matching +full:ports +full:- +full:offset2
1 // SPDX-License-Identifier: GPL-2.0
101 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
102 #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m)
103 #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1))
104 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m)
105 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m)
106 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m)
107 #define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m)
108 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1))
204 /* Port numbers are 1 - 14 */
283 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_read()
303 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_write()
323 *val = readl(ctrl->mmio + reg); in qcom_swrm_cpu_reg_read()
330 writel(val, ctrl->mmio + reg); in qcom_swrm_cpu_reg_write()
359 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_rd_fifo_avail()
368 } while (fifo_retry_count--); in swrm_wait_for_rd_fifo_avail()
371 dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__); in swrm_wait_for_rd_fifo_avail()
372 return -EIO; in swrm_wait_for_rd_fifo_avail()
385 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_wr_fifo_avail()
390 if (fifo_outstanding_cmds < ctrl->wr_fifo_depth) in swrm_wait_for_wr_fifo_avail()
394 } while (fifo_retry_count--); in swrm_wait_for_wr_fifo_avail()
396 if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) { in swrm_wait_for_wr_fifo_avail()
397 dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__); in swrm_wait_for_wr_fifo_avail()
398 return -EIO; in swrm_wait_for_wr_fifo_avail()
410 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); in swrm_wait_for_wr_fifo_done()
416 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); in swrm_wait_for_wr_fifo_done()
418 fifo_retry_count--; in swrm_wait_for_wr_fifo_done()
443 val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data, in qcom_swrm_cmd_fifo_wr_cmd()
451 reinit_completion(&ctrl->broadcast); in qcom_swrm_cmd_fifo_wr_cmd()
454 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val); in qcom_swrm_cmd_fifo_wr_cmd()
456 if (ctrl->version <= SWRM_VERSION_1_3_0) in qcom_swrm_cmd_fifo_wr_cmd()
465 ret = wait_for_completion_timeout(&ctrl->broadcast, in qcom_swrm_cmd_fifo_wr_cmd()
484 val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr); in qcom_swrm_cmd_fifo_rd_cmd()
494 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val); in qcom_swrm_cmd_fifo_rd_cmd()
502 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR], in qcom_swrm_cmd_fifo_rd_cmd()
507 if (cmd_id != ctrl->rcmd_id) { in qcom_swrm_cmd_fifo_rd_cmd()
508 if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) { in qcom_swrm_cmd_fifo_rd_cmd()
511 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, in qcom_swrm_cmd_fifo_rd_cmd()
513 ctrl->reg_write(ctrl, in qcom_swrm_cmd_fifo_rd_cmd()
514 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], in qcom_swrm_cmd_fifo_rd_cmd()
524 dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ in qcom_swrm_cmd_fifo_rd_cmd()
526 reg_addr, ctrl->rcmd_id, dev_addr, cmd_data); in qcom_swrm_cmd_fifo_rd_cmd()
536 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_alert_slave_dev_num()
542 ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK; in qcom_swrm_get_alert_slave_dev_num()
547 return -EINVAL; in qcom_swrm_get_alert_slave_dev_num()
555 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_device_status()
556 ctrl->slave_status = val; in qcom_swrm_get_device_status()
563 ctrl->status[i] = s; in qcom_swrm_get_device_status()
573 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status); in qcom_swrm_set_slave_dev_num()
579 slave->dev_num = devnum; in qcom_swrm_set_slave_dev_num()
580 mutex_lock(&bus->bus_lock); in qcom_swrm_set_slave_dev_num()
581 set_bit(devnum, bus->assigned); in qcom_swrm_set_slave_dev_num()
582 mutex_unlock(&bus->bus_lock); in qcom_swrm_set_slave_dev_num()
599 if (!ctrl->status[i]) in qcom_swrm_enumerate()
602 /*SCP_Devid5 - Devid 4*/ in qcom_swrm_enumerate()
603 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); in qcom_swrm_enumerate()
605 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/ in qcom_swrm_enumerate()
606 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2); in qcom_swrm_enumerate()
617 ctrl->clock_stop_not_supported = false; in qcom_swrm_enumerate()
619 list_for_each_entry_safe(slave, _s, &bus->slaves, node) { in qcom_swrm_enumerate()
622 if (slave->prop.clk_stop_mode1) in qcom_swrm_enumerate()
623 ctrl->clock_stop_not_supported = true; in qcom_swrm_enumerate()
636 complete(&ctrl->enumeration); in qcom_swrm_enumerate()
645 ret = pm_runtime_get_sync(ctrl->dev); in qcom_swrm_wake_irq_handler()
646 if (ret < 0 && ret != -EACCES) { in qcom_swrm_wake_irq_handler()
647 dev_err_ratelimited(ctrl->dev, in qcom_swrm_wake_irq_handler()
650 pm_runtime_put_noidle(ctrl->dev); in qcom_swrm_wake_irq_handler()
654 if (ctrl->wake_irq > 0) { in qcom_swrm_wake_irq_handler()
655 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) in qcom_swrm_wake_irq_handler()
656 disable_irq_nosync(ctrl->wake_irq); in qcom_swrm_wake_irq_handler()
659 pm_runtime_mark_last_busy(ctrl->dev); in qcom_swrm_wake_irq_handler()
660 pm_runtime_put_autosuspend(ctrl->dev); in qcom_swrm_wake_irq_handler()
672 clk_prepare_enable(ctrl->hclk); in qcom_swrm_irq_handler()
674 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], in qcom_swrm_irq_handler()
676 intr_sts_masked = intr_sts & ctrl->intr_mask; in qcom_swrm_irq_handler()
688 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
691 sdw_handle_slave_status(&ctrl->bus, ctrl->status); in qcom_swrm_irq_handler()
697 dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n"); in qcom_swrm_irq_handler()
698 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status); in qcom_swrm_irq_handler()
699 if (ctrl->slave_status == slave_status) { in qcom_swrm_irq_handler()
700 dev_dbg(ctrl->dev, "Slave status not changed %x\n", in qcom_swrm_irq_handler()
704 qcom_swrm_enumerate(&ctrl->bus); in qcom_swrm_irq_handler()
705 sdw_handle_slave_status(&ctrl->bus, ctrl->status); in qcom_swrm_irq_handler()
709 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
712 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; in qcom_swrm_irq_handler()
713 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
714 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
715 ctrl->intr_mask); in qcom_swrm_irq_handler()
718 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
719 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
721 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
726 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
727 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
729 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
734 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
735 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
737 dev_err(ctrl->dev, in qcom_swrm_irq_handler()
740 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
743 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
744 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
746 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
749 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
752 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
755 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; in qcom_swrm_irq_handler()
756 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
757 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
758 ctrl->intr_mask); in qcom_swrm_irq_handler()
761 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
764 ctrl->intr_mask &= in qcom_swrm_irq_handler()
766 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
767 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
768 ctrl->intr_mask); in qcom_swrm_irq_handler()
771 complete(&ctrl->broadcast); in qcom_swrm_irq_handler()
780 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
787 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], in qcom_swrm_irq_handler()
789 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], in qcom_swrm_irq_handler()
791 intr_sts_masked = intr_sts & ctrl->intr_mask; in qcom_swrm_irq_handler()
794 clk_disable_unprepare(ctrl->hclk); in qcom_swrm_irq_handler()
804 ctrl->reg_read(ctrl, SWRM_COMP_STATUS, &comp_sts); in swrm_wait_for_frame_gen_enabled()
810 } while (retry--); in swrm_wait_for_frame_gen_enabled()
812 dev_err(ctrl->dev, "%s: link status not %s\n", __func__, in swrm_wait_for_frame_gen_enabled()
823 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); in qcom_swrm_init()
824 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); in qcom_swrm_init()
826 reset_control_reset(ctrl->audio_cgcr); in qcom_swrm_init()
828 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); in qcom_swrm_init()
831 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1); in qcom_swrm_init()
833 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; in qcom_swrm_init()
835 if (ctrl->version < SWRM_VERSION_2_0_0) in qcom_swrm_init()
836 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], in qcom_swrm_init()
840 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); in qcom_swrm_init()
842 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); in qcom_swrm_init()
844 if (ctrl->version == SWRM_VERSION_1_7_0) { in qcom_swrm_init()
845 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); in qcom_swrm_init()
846 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, in qcom_swrm_init()
848 } else if (ctrl->version >= SWRM_VERSION_2_0_0) { in qcom_swrm_init()
849 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); in qcom_swrm_init()
850 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, in qcom_swrm_init()
853 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); in qcom_swrm_init()
857 if (ctrl->version >= SWRM_VERSION_1_5_1) { in qcom_swrm_init()
858 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, in qcom_swrm_init()
862 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, in qcom_swrm_init()
867 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK); in qcom_swrm_init()
870 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, in qcom_swrm_init()
873 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], in qcom_swrm_init()
877 if (ctrl->mmio) { in qcom_swrm_init()
878 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_init()
883 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, in qcom_swrm_init()
888 ctrl->slave_status = 0; in qcom_swrm_init()
889 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); in qcom_swrm_init()
890 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val); in qcom_swrm_init()
891 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val); in qcom_swrm_init()
902 if (msg->flags == SDW_MSG_FLAG_READ) { in qcom_swrm_xfer_msg()
903 for (i = 0; i < msg->len;) { in qcom_swrm_xfer_msg()
904 if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN) in qcom_swrm_xfer_msg()
905 len = msg->len - i; in qcom_swrm_xfer_msg()
909 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num, in qcom_swrm_xfer_msg()
910 msg->addr + i, len, in qcom_swrm_xfer_msg()
911 &msg->buf[i]); in qcom_swrm_xfer_msg()
917 } else if (msg->flags == SDW_MSG_FLAG_WRITE) { in qcom_swrm_xfer_msg()
918 for (i = 0; i < msg->len; i++) { in qcom_swrm_xfer_msg()
919 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i], in qcom_swrm_xfer_msg()
920 msg->dev_num, in qcom_swrm_xfer_msg()
921 msg->addr + i); in qcom_swrm_xfer_msg()
932 u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank); in qcom_swrm_pre_bank_switch()
936 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_pre_bank_switch()
938 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK); in qcom_swrm_pre_bank_switch()
939 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK); in qcom_swrm_pre_bank_switch()
941 return ctrl->reg_write(ctrl, reg, val); in qcom_swrm_pre_bank_switch()
950 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num), in qcom_swrm_port_params()
951 p_params->bps - 1); in qcom_swrm_port_params()
962 int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank); in qcom_swrm_transport_params()
965 pcfg = &ctrl->pconfig[params->port_num]; in qcom_swrm_transport_params()
967 value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT; in qcom_swrm_transport_params()
968 value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT; in qcom_swrm_transport_params()
969 value |= pcfg->si & 0xff; in qcom_swrm_transport_params()
971 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
975 if (pcfg->si > 0xff) { in qcom_swrm_transport_params()
976 value = (pcfg->si >> 8) & 0xff; in qcom_swrm_transport_params()
977 reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank); in qcom_swrm_transport_params()
978 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
983 if (pcfg->lane_control != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
984 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank); in qcom_swrm_transport_params()
985 value = pcfg->lane_control; in qcom_swrm_transport_params()
986 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
991 if (pcfg->blk_group_count != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
992 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank); in qcom_swrm_transport_params()
993 value = pcfg->blk_group_count; in qcom_swrm_transport_params()
994 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
999 if (pcfg->hstart != SWR_INVALID_PARAM in qcom_swrm_transport_params()
1000 && pcfg->hstop != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
1001 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); in qcom_swrm_transport_params()
1002 value = (pcfg->hstop << 4) | pcfg->hstart; in qcom_swrm_transport_params()
1003 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1005 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); in qcom_swrm_transport_params()
1007 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1013 if (pcfg->bp_mode != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
1014 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank); in qcom_swrm_transport_params()
1015 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode); in qcom_swrm_transport_params()
1026 u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank); in qcom_swrm_port_enable()
1030 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_port_enable()
1032 if (enable_ch->enable) in qcom_swrm_port_enable()
1033 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); in qcom_swrm_port_enable()
1037 return ctrl->reg_write(ctrl, reg, val); in qcom_swrm_port_enable()
1062 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { in qcom_swrm_compute_params()
1063 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { in qcom_swrm_compute_params()
1064 pcfg = &ctrl->pconfig[p_rt->num]; in qcom_swrm_compute_params()
1065 p_rt->transport_params.port_num = p_rt->num; in qcom_swrm_compute_params()
1066 if (pcfg->word_length != SWR_INVALID_PARAM) { in qcom_swrm_compute_params()
1067 sdw_fill_port_params(&p_rt->port_params, in qcom_swrm_compute_params()
1068 p_rt->num, pcfg->word_length + 1, in qcom_swrm_compute_params()
1075 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in qcom_swrm_compute_params()
1076 slave = s_rt->slave; in qcom_swrm_compute_params()
1077 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in qcom_swrm_compute_params()
1078 m_port = slave->m_port_map[p_rt->num]; in qcom_swrm_compute_params()
1079 /* port config starts at offset 0 so -1 from actual port number */ in qcom_swrm_compute_params()
1081 pcfg = &ctrl->pconfig[m_port]; in qcom_swrm_compute_params()
1083 pcfg = &ctrl->pconfig[i]; in qcom_swrm_compute_params()
1084 p_rt->transport_params.port_num = p_rt->num; in qcom_swrm_compute_params()
1085 p_rt->transport_params.sample_interval = in qcom_swrm_compute_params()
1086 pcfg->si + 1; in qcom_swrm_compute_params()
1087 p_rt->transport_params.offset1 = pcfg->off1; in qcom_swrm_compute_params()
1088 p_rt->transport_params.offset2 = pcfg->off2; in qcom_swrm_compute_params()
1089 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode; in qcom_swrm_compute_params()
1090 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count; in qcom_swrm_compute_params()
1092 p_rt->transport_params.hstart = pcfg->hstart; in qcom_swrm_compute_params()
1093 p_rt->transport_params.hstop = pcfg->hstop; in qcom_swrm_compute_params()
1094 p_rt->transport_params.lane_ctrl = pcfg->lane_control; in qcom_swrm_compute_params()
1095 if (pcfg->word_length != SWR_INVALID_PARAM) { in qcom_swrm_compute_params()
1096 sdw_fill_port_params(&p_rt->port_params, in qcom_swrm_compute_params()
1097 p_rt->num, in qcom_swrm_compute_params()
1098 pcfg->word_length + 1, in qcom_swrm_compute_params()
1121 mutex_lock(&ctrl->port_lock); in qcom_swrm_stream_free_ports()
1123 list_for_each_entry(m_rt, &stream->master_list, stream_node) { in qcom_swrm_stream_free_ports()
1124 if (m_rt->direction == SDW_DATA_DIR_RX) in qcom_swrm_stream_free_ports()
1125 port_mask = &ctrl->dout_port_mask; in qcom_swrm_stream_free_ports()
1127 port_mask = &ctrl->din_port_mask; in qcom_swrm_stream_free_ports()
1129 list_for_each_entry(p_rt, &m_rt->port_list, port_node) in qcom_swrm_stream_free_ports()
1130 clear_bit(p_rt->num, port_mask); in qcom_swrm_stream_free_ports()
1133 mutex_unlock(&ctrl->port_lock); in qcom_swrm_stream_free_ports()
1151 mutex_lock(&ctrl->port_lock); in qcom_swrm_stream_alloc_ports()
1152 list_for_each_entry(m_rt, &stream->master_list, stream_node) { in qcom_swrm_stream_alloc_ports()
1153 if (m_rt->direction == SDW_DATA_DIR_RX) { in qcom_swrm_stream_alloc_ports()
1154 maxport = ctrl->num_dout_ports; in qcom_swrm_stream_alloc_ports()
1155 port_mask = &ctrl->dout_port_mask; in qcom_swrm_stream_alloc_ports()
1157 maxport = ctrl->num_din_ports; in qcom_swrm_stream_alloc_ports()
1158 port_mask = &ctrl->din_port_mask; in qcom_swrm_stream_alloc_ports()
1161 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in qcom_swrm_stream_alloc_ports()
1162 slave = s_rt->slave; in qcom_swrm_stream_alloc_ports()
1163 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in qcom_swrm_stream_alloc_ports()
1164 m_port = slave->m_port_map[p_rt->num]; in qcom_swrm_stream_alloc_ports()
1165 /* Port numbers start from 1 - 14*/ in qcom_swrm_stream_alloc_ports()
1172 dev_err(ctrl->dev, "All ports busy\n"); in qcom_swrm_stream_alloc_ports()
1173 ret = -EBUSY; in qcom_swrm_stream_alloc_ports()
1178 pconfig[nports].ch_mask = p_rt->ch_mask; in qcom_swrm_stream_alloc_ports()
1192 sconfig.type = stream->type; in qcom_swrm_stream_alloc_ports()
1194 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig, in qcom_swrm_stream_alloc_ports()
1202 mutex_unlock(&ctrl->port_lock); in qcom_swrm_stream_alloc_ports()
1211 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_hw_params()
1212 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; in qcom_swrm_hw_params()
1216 substream->stream); in qcom_swrm_hw_params()
1226 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_hw_free()
1227 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; in qcom_swrm_hw_free()
1230 sdw_stream_remove_master(&ctrl->bus, sruntime); in qcom_swrm_hw_free()
1238 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_set_sdw_stream()
1240 ctrl->sruntime[dai->id] = stream; in qcom_swrm_set_sdw_stream()
1247 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_get_sdw_stream()
1249 return ctrl->sruntime[dai->id]; in qcom_swrm_get_sdw_stream()
1255 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_startup()
1256 struct snd_soc_pcm_runtime *rtd = substream->private_data; in qcom_swrm_startup()
1261 ret = pm_runtime_get_sync(ctrl->dev); in qcom_swrm_startup()
1262 if (ret < 0 && ret != -EACCES) { in qcom_swrm_startup()
1263 dev_err_ratelimited(ctrl->dev, in qcom_swrm_startup()
1266 pm_runtime_put_noidle(ctrl->dev); in qcom_swrm_startup()
1270 sruntime = sdw_alloc_stream(dai->name); in qcom_swrm_startup()
1272 ret = -ENOMEM; in qcom_swrm_startup()
1276 ctrl->sruntime[dai->id] = sruntime; in qcom_swrm_startup()
1280 substream->stream); in qcom_swrm_startup()
1281 if (ret < 0 && ret != -ENOTSUPP) { in qcom_swrm_startup()
1282 dev_err(dai->dev, "Failed to set sdw stream on %s\n", in qcom_swrm_startup()
1283 codec_dai->name); in qcom_swrm_startup()
1293 pm_runtime_mark_last_busy(ctrl->dev); in qcom_swrm_startup()
1294 pm_runtime_put_autosuspend(ctrl->dev); in qcom_swrm_startup()
1302 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_shutdown()
1305 sdw_release_stream(ctrl->sruntime[dai->id]); in qcom_swrm_shutdown()
1306 ctrl->sruntime[dai->id] = NULL; in qcom_swrm_shutdown()
1307 pm_runtime_mark_last_busy(ctrl->dev); in qcom_swrm_shutdown()
1308 pm_runtime_put_autosuspend(ctrl->dev); in qcom_swrm_shutdown()
1327 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_register_dais()
1330 struct device *dev = ctrl->dev; in qcom_swrm_register_dais()
1336 return -ENOMEM; in qcom_swrm_register_dais()
1341 return -ENOMEM; in qcom_swrm_register_dais()
1343 if (i < ctrl->num_dout_ports) in qcom_swrm_register_dais()
1348 stream->channels_min = 1; in qcom_swrm_register_dais()
1349 stream->channels_max = 1; in qcom_swrm_register_dais()
1350 stream->rates = SNDRV_PCM_RATE_48000; in qcom_swrm_register_dais()
1351 stream->formats = SNDRV_PCM_FMTBIT_S16_LE; in qcom_swrm_register_dais()
1357 return devm_snd_soc_register_component(ctrl->dev, in qcom_swrm_register_dais()
1364 struct device_node *np = ctrl->dev->of_node; in qcom_swrm_get_port_config()
1377 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); in qcom_swrm_get_port_config()
1379 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val); in qcom_swrm_get_port_config()
1380 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val); in qcom_swrm_get_port_config()
1382 ret = of_property_read_u32(np, "qcom,din-ports", &val); in qcom_swrm_get_port_config()
1386 if (val > ctrl->num_din_ports) in qcom_swrm_get_port_config()
1387 return -EINVAL; in qcom_swrm_get_port_config()
1389 ctrl->num_din_ports = val; in qcom_swrm_get_port_config()
1391 ret = of_property_read_u32(np, "qcom,dout-ports", &val); in qcom_swrm_get_port_config()
1395 if (val > ctrl->num_dout_ports) in qcom_swrm_get_port_config()
1396 return -EINVAL; in qcom_swrm_get_port_config()
1398 ctrl->num_dout_ports = val; in qcom_swrm_get_port_config()
1400 nports = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_get_port_config()
1402 return -EINVAL; in qcom_swrm_get_port_config()
1404 /* Valid port numbers are from 1-14, so mask out port 0 explicitly */ in qcom_swrm_get_port_config()
1405 set_bit(0, &ctrl->dout_port_mask); in qcom_swrm_get_port_config()
1406 set_bit(0, &ctrl->din_port_mask); in qcom_swrm_get_port_config()
1408 ret = of_property_read_u8_array(np, "qcom,ports-offset1", in qcom_swrm_get_port_config()
1413 ret = of_property_read_u8_array(np, "qcom,ports-offset2", in qcom_swrm_get_port_config()
1418 ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low", in qcom_swrm_get_port_config()
1421 ret = of_property_read_u16_array(np, "qcom,ports-sinterval", in qcom_swrm_get_port_config()
1428 ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode", in qcom_swrm_get_port_config()
1431 if (ctrl->version <= SWRM_VERSION_1_3_0) in qcom_swrm_get_port_config()
1438 of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports); in qcom_swrm_get_port_config()
1441 of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports); in qcom_swrm_get_port_config()
1444 of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports); in qcom_swrm_get_port_config()
1447 of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports); in qcom_swrm_get_port_config()
1450 of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports); in qcom_swrm_get_port_config()
1453 /* Valid port number range is from 1-14 */ in qcom_swrm_get_port_config()
1455 ctrl->pconfig[i + 1].si = si[i]; in qcom_swrm_get_port_config()
1457 ctrl->pconfig[i + 1].si = ((u8 *)si)[i]; in qcom_swrm_get_port_config()
1458 ctrl->pconfig[i + 1].off1 = off1[i]; in qcom_swrm_get_port_config()
1459 ctrl->pconfig[i + 1].off2 = off2[i]; in qcom_swrm_get_port_config()
1460 ctrl->pconfig[i + 1].bp_mode = bp_mode[i]; in qcom_swrm_get_port_config()
1461 ctrl->pconfig[i + 1].hstart = hstart[i]; in qcom_swrm_get_port_config()
1462 ctrl->pconfig[i + 1].hstop = hstop[i]; in qcom_swrm_get_port_config()
1463 ctrl->pconfig[i + 1].word_length = word_length[i]; in qcom_swrm_get_port_config()
1464 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i]; in qcom_swrm_get_port_config()
1465 ctrl->pconfig[i + 1].lane_control = lane_control[i]; in qcom_swrm_get_port_config()
1474 struct qcom_swrm_ctrl *ctrl = s_file->private; in swrm_reg_show()
1477 ret = pm_runtime_get_sync(ctrl->dev); in swrm_reg_show()
1478 if (ret < 0 && ret != -EACCES) { in swrm_reg_show()
1479 dev_err_ratelimited(ctrl->dev, in swrm_reg_show()
1482 pm_runtime_put_noidle(ctrl->dev); in swrm_reg_show()
1486 for (reg = 0; reg <= ctrl->max_reg; reg += 4) { in swrm_reg_show()
1487 ctrl->reg_read(ctrl, reg, ®_val); in swrm_reg_show()
1490 pm_runtime_mark_last_busy(ctrl->dev); in swrm_reg_show()
1491 pm_runtime_put_autosuspend(ctrl->dev); in swrm_reg_show()
1501 struct device *dev = &pdev->dev;
1511 return -ENOMEM;
1514 ctrl->max_reg = data->max_reg;
1515 ctrl->reg_layout = data->reg_layout;
1516 ctrl->rows_index = sdw_find_row_index(data->default_rows);
1517 ctrl->cols_index = sdw_find_col_index(data->default_cols);
1519 if (dev->parent->bus == &slimbus_bus) {
1523 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1524 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1525 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1526 if (!ctrl->regmap)
1527 return -EINVAL;
1529 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1530 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1531 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1532 if (IS_ERR(ctrl->mmio))
1533 return PTR_ERR(ctrl->mmio);
1536 if (data->sw_clk_gate_required) {
1537 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
1538 if (IS_ERR(ctrl->audio_cgcr)) {
1540 ret = PTR_ERR(ctrl->audio_cgcr);
1545 ctrl->irq = of_irq_get(dev->of_node, 0);
1546 if (ctrl->irq < 0) {
1547 ret = ctrl->irq;
1551 ctrl->hclk = devm_clk_get(dev, "iface");
1552 if (IS_ERR(ctrl->hclk)) {
1553 ret = PTR_ERR(ctrl->hclk);
1557 clk_prepare_enable(ctrl->hclk);
1559 ctrl->dev = dev;
1560 dev_set_drvdata(&pdev->dev, ctrl);
1561 mutex_init(&ctrl->port_lock);
1562 init_completion(&ctrl->broadcast);
1563 init_completion(&ctrl->enumeration);
1565 ctrl->bus.ops = &qcom_swrm_ops;
1566 ctrl->bus.port_ops = &qcom_swrm_port_ops;
1567 ctrl->bus.compute_params = &qcom_swrm_compute_params;
1568 ctrl->bus.clk_stop_timeout = 300;
1574 params = &ctrl->bus.params;
1575 params->max_dr_freq = DEFAULT_CLK_FREQ;
1576 params->curr_dr_freq = DEFAULT_CLK_FREQ;
1577 params->col = data->default_cols;
1578 params->row = data->default_rows;
1579 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1580 params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1581 params->next_bank = !params->curr_bank;
1583 prop = &ctrl->bus.prop;
1584 prop->max_clk_freq = DEFAULT_CLK_FREQ;
1585 prop->num_clk_gears = 0;
1586 prop->num_clk_freq = MAX_FREQ_NUM;
1587 prop->clk_freq = &qcom_swrm_freq_tbl[0];
1588 prop->default_col = data->default_cols;
1589 prop->default_row = data->default_rows;
1591 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1593 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1603 ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1604 if (ctrl->wake_irq > 0) {
1605 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1615 /* FIXME: is there a DT-defined value to use ? */
1616 ctrl->bus.controller_id = -1;
1618 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1626 wait_for_completion_timeout(&ctrl->enumeration,
1633 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1634 ctrl->version & 0xffff);
1643 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1644 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1651 sdw_bus_master_delete(&ctrl->bus);
1653 clk_disable_unprepare(ctrl->hclk);
1660 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1662 sdw_bus_master_delete(&ctrl->bus);
1663 clk_disable_unprepare(ctrl->hclk);
1673 if (ctrl->wake_irq > 0) {
1674 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1675 disable_irq_nosync(ctrl->wake_irq);
1678 clk_prepare_enable(ctrl->hclk);
1680 if (ctrl->clock_stop_not_supported) {
1681 reinit_completion(&ctrl->enumeration);
1682 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1689 dev_err(ctrl->dev, "link failed to connect\n");
1692 wait_for_completion_timeout(&ctrl->enumeration,
1695 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1697 reset_control_reset(ctrl->audio_cgcr);
1699 if (ctrl->version == SWRM_VERSION_1_7_0) {
1700 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1701 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1703 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
1704 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1705 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1708 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1710 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1713 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1714 if (ctrl->version < SWRM_VERSION_2_0_0)
1715 ctrl->reg_write(ctrl,
1716 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1717 ctrl->intr_mask);
1718 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1719 ctrl->intr_mask);
1723 dev_err(ctrl->dev, "link failed to connect\n");
1725 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1727 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1739 if (!ctrl->clock_stop_not_supported) {
1741 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1742 if (ctrl->version < SWRM_VERSION_2_0_0)
1743 ctrl->reg_write(ctrl,
1744 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1745 ctrl->intr_mask);
1746 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1747 ctrl->intr_mask);
1749 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1750 if (ret < 0 && ret != -ENODATA) {
1755 ret = sdw_bus_clk_stop(&ctrl->bus);
1756 if (ret < 0 && ret != -ENODATA) {
1762 clk_disable_unprepare(ctrl->hclk);
1766 if (ctrl->wake_irq > 0) {
1767 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1768 enable_irq(ctrl->wake_irq);
1779 { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1780 { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1781 { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
1782 { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data },
1783 { .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data },
1793 .name = "qcom-soundwire",