Lines Matching refs:lane_ctrl_ch_en_reg
484 u32 offset_reg, lane_ctrl_ch_en_reg; in amd_sdw_transport_params() local
492 lane_ctrl_ch_en_reg = sdw0_manager_dp_reg[params->port_num].lane_ctrl_ch_en_reg; in amd_sdw_transport_params()
499 lane_ctrl_ch_en_reg = sdw1_manager_dp_reg[params->port_num].lane_ctrl_ch_en_reg; in amd_sdw_transport_params()
527 dpn_lanectrl = readl(amd_manager->mmio + lane_ctrl_ch_en_reg); in amd_sdw_transport_params()
529 writel(dpn_lanectrl, amd_manager->mmio + lane_ctrl_ch_en_reg); in amd_sdw_transport_params()
539 u32 lane_ctrl_ch_en_reg; in amd_sdw_port_enable() local
543 lane_ctrl_ch_en_reg = sdw0_manager_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; in amd_sdw_port_enable()
546 lane_ctrl_ch_en_reg = sdw1_manager_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg; in amd_sdw_port_enable()
556 dpn_ch_enable = readl(amd_manager->mmio + lane_ctrl_ch_en_reg); in amd_sdw_port_enable()
559 writel(dpn_ch_enable, amd_manager->mmio + lane_ctrl_ch_en_reg); in amd_sdw_port_enable()
561 writel(0, amd_manager->mmio + lane_ctrl_ch_en_reg); in amd_sdw_port_enable()