Lines Matching refs:core_min_uV
30 int core_min_uV, cpu_min_uV; member
46 int core_min_uV = 0; in tegra30_core_limit() local
66 if (tegra->core_min_uV > 0) in tegra30_core_limit()
67 return tegra->core_min_uV; in tegra30_core_limit()
75 err = regulator_check_voltage(core_rdev, &core_min_uV, &core_max_uV); in tegra30_core_limit()
84 tegra->core_min_uV = core_max_uV; in tegra30_core_limit()
86 pr_info("core voltage initialized to %duV\n", tegra->core_min_uV); in tegra30_core_limit()
88 return tegra->core_min_uV; in tegra30_core_limit()
170 int core_min_uV, core_max_uV = INT_MAX; in tegra30_voltage_update() local
212 core_min_uV = tegra30_core_limit(tegra, core_rdev); in tegra30_voltage_update()
213 if (core_min_uV < 0) in tegra30_voltage_update()
214 return core_min_uV; in tegra30_voltage_update()
216 err = regulator_check_consumers(core_rdev, &core_min_uV, &core_max_uV, in tegra30_voltage_update()
223 core_min_uV = clamp(tegra30_core_nominal_uV(), in tegra30_voltage_update()
224 core_min_uV, core_max_uV); in tegra30_voltage_update()
230 cpu_min_uV = core_min_uV - max_spread; in tegra30_voltage_update()
271 core_min_uV = max(core_min_uV, tegra30_core_cpu_limit(cpu_min_uV)); in tegra30_voltage_update()
273 err = regulator_check_voltage(core_rdev, &core_min_uV, &core_max_uV); in tegra30_voltage_update()
292 while (cpu_uV != cpu_min_uV || core_uV != core_min_uV) { in tegra30_voltage_update()
316 core_target_uV = max(core_min_limited_uV, core_min_uV); in tegra30_voltage_update()