Lines Matching refs:pmc
269 struct tegra_pmc *pmc; member
357 void (*init)(struct tegra_pmc *pmc);
358 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
361 void (*set_wake_filters)(struct tegra_pmc *pmc);
364 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
472 static struct tegra_pmc *pmc = &(struct tegra_pmc) { variable
483 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) in tegra_pmc_readl() argument
487 if (pmc->tz_only) { in tegra_pmc_readl()
491 if (pmc->dev) in tegra_pmc_readl()
492 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_readl()
502 return readl(pmc->base + offset); in tegra_pmc_readl()
505 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, in tegra_pmc_writel() argument
510 if (pmc->tz_only) { in tegra_pmc_writel()
514 if (pmc->dev) in tegra_pmc_writel()
515 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_writel()
522 writel(value, pmc->base + offset); in tegra_pmc_writel()
526 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) in tegra_pmc_scratch_readl() argument
528 if (pmc->tz_only) in tegra_pmc_scratch_readl()
529 return tegra_pmc_readl(pmc, offset); in tegra_pmc_scratch_readl()
531 return readl(pmc->scratch + offset); in tegra_pmc_scratch_readl()
534 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, in tegra_pmc_scratch_writel() argument
537 if (pmc->tz_only) in tegra_pmc_scratch_writel()
538 tegra_pmc_writel(pmc, value, offset); in tegra_pmc_scratch_writel()
540 writel(value, pmc->scratch + offset); in tegra_pmc_scratch_writel()
550 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_state()
551 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; in tegra_powergate_state()
553 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; in tegra_powergate_state()
556 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) in tegra_powergate_is_valid() argument
558 return (pmc->soc && pmc->soc->powergates[id]); in tegra_powergate_is_valid()
561 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) in tegra_powergate_is_available() argument
563 return test_bit(id, pmc->powergates_available); in tegra_powergate_is_available()
566 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) in tegra_powergate_lookup() argument
570 if (!pmc || !pmc->soc || !name) in tegra_powergate_lookup()
573 for (i = 0; i < pmc->soc->num_powergates; i++) { in tegra_powergate_lookup()
574 if (!tegra_powergate_is_valid(pmc, i)) in tegra_powergate_lookup()
577 if (!strcmp(name, pmc->soc->powergates[i])) in tegra_powergate_lookup()
584 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id, in tegra20_powergate_set() argument
597 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); in tegra20_powergate_set()
607 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc) in tegra_powergate_toggle_ready() argument
609 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START); in tegra_powergate_toggle_ready()
612 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id, in tegra114_powergate_set() argument
619 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, in tegra114_powergate_set()
624 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); in tegra114_powergate_set()
627 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, in tegra114_powergate_set()
647 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, in tegra_powergate_set() argument
652 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_set()
655 mutex_lock(&pmc->powergates_lock); in tegra_powergate_set()
658 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
662 err = pmc->soc->powergate_set(pmc, id, new_state); in tegra_powergate_set()
664 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
669 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, in __tegra_powergate_remove_clamping() argument
674 mutex_lock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
681 if (pmc->soc->has_gpu_clamps) { in __tegra_powergate_remove_clamping()
682 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); in __tegra_powergate_remove_clamping()
698 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); in __tegra_powergate_remove_clamping()
701 mutex_unlock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
796 err = tegra_powergate_set(pg->pmc, pg->id, true); in tegra_powergate_power_up()
812 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); in tegra_powergate_power_up()
824 if (pg->pmc->soc->needs_mbist_war) in tegra_powergate_power_up()
846 tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_up()
875 err = tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_down()
903 struct device *dev = pg->pmc->dev; in tegra_genpd_power_on()
922 struct device *dev = pg->pmc->dev; in tegra_genpd_power_off()
948 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_power_on()
951 return tegra_powergate_set(pmc, id, true); in tegra_powergate_power_on()
961 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_power_off()
964 return tegra_powergate_set(pmc, id, false); in tegra_powergate_power_off()
973 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) in tegra_powergate_is_powered() argument
975 if (!tegra_powergate_is_valid(pmc, id)) in tegra_powergate_is_powered()
987 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_remove_clamping()
990 return __tegra_powergate_remove_clamping(pmc, id); in tegra_powergate_remove_clamping()
1008 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_sequence_power_up()
1025 pg->pmc = pmc; in tegra_powergate_sequence_power_up()
1029 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, in tegra_powergate_sequence_power_up()
1047 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, in tegra_get_cpu_powergate_id() argument
1050 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) in tegra_get_cpu_powergate_id()
1051 return pmc->soc->cpu_powergates[cpuid]; in tegra_get_cpu_powergate_id()
1064 id = tegra_get_cpu_powergate_id(pmc, cpuid); in tegra_pmc_cpu_is_powered()
1068 return tegra_powergate_is_powered(pmc, id); in tegra_pmc_cpu_is_powered()
1079 id = tegra_get_cpu_powergate_id(pmc, cpuid); in tegra_pmc_cpu_power_on()
1083 return tegra_powergate_set(pmc, id, true); in tegra_pmc_cpu_power_on()
1094 id = tegra_get_cpu_powergate_id(pmc, cpuid); in tegra_pmc_cpu_remove_clamping()
1105 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); in tegra_pmc_program_reboot_reason()
1119 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); in tegra_pmc_program_reboot_reason()
1140 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra_pmc_restart()
1142 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra_pmc_restart()
1162 tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37); in tegra_pmc_power_off_handler()
1177 for (i = 0; i < pmc->soc->num_powergates; i++) { in powergate_show()
1178 status = tegra_powergate_is_powered(pmc, i); in powergate_show()
1182 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], in powergate_show()
1237 struct device *dev = pg->pmc->dev; in tegra_powergate_of_get_resets()
1272 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) in tegra_powergate_add() argument
1274 struct device *dev = pmc->dev; in tegra_powergate_add()
1283 id = tegra_powergate_lookup(pmc, np->name); in tegra_powergate_add()
1294 clear_bit(id, pmc->powergates_available); in tegra_powergate_add()
1300 pg->pmc = pmc; in tegra_powergate_add()
1302 off = !tegra_powergate_is_powered(pmc, pg->id); in tegra_powergate_add()
1354 set_bit(id, pmc->powergates_available); in tegra_powergate_add()
1364 return pmc->core_domain_state_synced; in tegra_pmc_core_domain_state_synced()
1381 mutex_lock(&pmc->powergates_lock); in tegra_pmc_core_pd_set_performance_state()
1382 err = dev_pm_opp_set_opp(pmc->dev, opp); in tegra_pmc_core_pd_set_performance_state()
1383 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_core_pd_set_performance_state()
1403 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) in tegra_pmc_core_pd_add() argument
1409 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL); in tegra_pmc_core_pd_add()
1417 err = devm_pm_opp_set_regulators(pmc->dev, rname); in tegra_pmc_core_pd_add()
1419 return dev_err_probe(pmc->dev, err, in tegra_pmc_core_pd_add()
1424 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); in tegra_pmc_core_pd_add()
1430 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); in tegra_pmc_core_pd_add()
1434 pmc->core_domain_registered = true; in tegra_pmc_core_pd_add()
1444 static int tegra_powergate_init(struct tegra_pmc *pmc, in tegra_powergate_init() argument
1457 err = tegra_pmc_core_pd_add(pmc, np); in tegra_powergate_init()
1468 err = tegra_powergate_add(pmc, child); in tegra_powergate_init()
1506 set_bit(pg->id, pmc->powergates_available); in tegra_powergate_remove()
1540 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) in tegra_io_pad_find() argument
1544 for (i = 0; i < pmc->soc->num_io_pads; i++) in tegra_io_pad_find()
1545 if (pmc->soc->io_pads[i].id == id) in tegra_io_pad_find()
1546 return &pmc->soc->io_pads[i]; in tegra_io_pad_find()
1551 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, in tegra_io_pad_prepare() argument
1566 if (pmc->clk) { in tegra_io_pad_prepare()
1567 rate = pmc->rate; in tegra_io_pad_prepare()
1569 dev_err(pmc->dev, "failed to get clock rate\n"); in tegra_io_pad_prepare()
1573 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); in tegra_io_pad_prepare()
1578 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); in tegra_io_pad_prepare()
1584 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, in tegra_io_pad_poll() argument
1592 value = tegra_pmc_readl(pmc, offset); in tegra_io_pad_poll()
1602 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) in tegra_io_pad_unprepare() argument
1604 if (pmc->clk) in tegra_io_pad_unprepare()
1605 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); in tegra_io_pad_unprepare()
1621 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_power_enable()
1623 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_power_enable()
1627 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1629 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); in tegra_io_pad_power_enable()
1631 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1635 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); in tegra_io_pad_power_enable()
1637 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); in tegra_io_pad_power_enable()
1639 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1643 tegra_io_pad_unprepare(pmc); in tegra_io_pad_power_enable()
1646 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1664 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_power_disable()
1666 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_power_disable()
1670 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1672 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); in tegra_io_pad_power_disable()
1674 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1678 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); in tegra_io_pad_power_disable()
1680 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); in tegra_io_pad_power_disable()
1682 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1686 tegra_io_pad_unprepare(pmc); in tegra_io_pad_power_disable()
1689 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1694 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) in tegra_io_pad_is_powered() argument
1700 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_is_powered()
1702 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_is_powered()
1712 value = tegra_pmc_readl(pmc, status); in tegra_io_pad_is_powered()
1717 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, in tegra_io_pad_set_voltage() argument
1723 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_set_voltage()
1730 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1732 if (pmc->soc->has_impl_33v_pwr) { in tegra_io_pad_set_voltage()
1733 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); in tegra_io_pad_set_voltage()
1740 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); in tegra_io_pad_set_voltage()
1743 value = tegra_pmc_readl(pmc, PMC_PWR_DET); in tegra_io_pad_set_voltage()
1745 tegra_pmc_writel(pmc, value, PMC_PWR_DET); in tegra_io_pad_set_voltage()
1748 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); in tegra_io_pad_set_voltage()
1755 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); in tegra_io_pad_set_voltage()
1758 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1765 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) in tegra_io_pad_get_voltage() argument
1770 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_get_voltage()
1777 if (pmc->soc->has_impl_33v_pwr) in tegra_io_pad_get_voltage()
1778 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); in tegra_io_pad_get_voltage()
1780 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); in tegra_io_pad_get_voltage()
1815 return pmc->suspend_mode; in tegra_pmc_get_suspend_mode()
1823 pmc->suspend_mode = mode; in tegra_pmc_set_suspend_mode()
1838 rate = pmc->rate; in tegra_pmc_enter_suspend_mode()
1848 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1850 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); in tegra_pmc_enter_suspend_mode()
1852 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1854 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); in tegra_pmc_enter_suspend_mode()
1856 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra_pmc_enter_suspend_mode()
1859 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra_pmc_enter_suspend_mode()
1863 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) in tegra_pmc_parse_dt() argument
1868 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1872 pmc->suspend_mode = TEGRA_SUSPEND_LP0; in tegra_pmc_parse_dt()
1876 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1880 pmc->suspend_mode = TEGRA_SUSPEND_LP2; in tegra_pmc_parse_dt()
1884 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1889 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); in tegra_pmc_parse_dt()
1892 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1894 pmc->cpu_good_time = value; in tegra_pmc_parse_dt()
1897 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1899 pmc->cpu_off_time = value; in tegra_pmc_parse_dt()
1903 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1905 pmc->core_osc_time = values[0]; in tegra_pmc_parse_dt()
1906 pmc->core_pmu_time = values[1]; in tegra_pmc_parse_dt()
1909 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1911 pmc->core_off_time = value; in tegra_pmc_parse_dt()
1913 pmc->corereq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1916 pmc->sysclkreq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1919 pmc->combined_req = of_property_read_bool(np, in tegra_pmc_parse_dt()
1922 pmc->cpu_pwr_good_en = of_property_read_bool(np, in tegra_pmc_parse_dt()
1927 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) in tegra_pmc_parse_dt()
1928 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1930 pmc->lp0_vec_phys = values[0]; in tegra_pmc_parse_dt()
1931 pmc->lp0_vec_size = values[1]; in tegra_pmc_parse_dt()
1936 static int tegra_pmc_init(struct tegra_pmc *pmc) in tegra_pmc_init() argument
1938 if (pmc->soc->max_wake_events > 0) { in tegra_pmc_init()
1939 pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1940 if (!pmc->wake_type_level_map) in tegra_pmc_init()
1943 pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1944 if (!pmc->wake_type_dual_edge_map) in tegra_pmc_init()
1947 pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1948 if (!pmc->wake_sw_status_map) in tegra_pmc_init()
1951 pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); in tegra_pmc_init()
1952 if (!pmc->wake_cntrl_level_map) in tegra_pmc_init()
1956 if (pmc->soc->init) in tegra_pmc_init()
1957 pmc->soc->init(pmc); in tegra_pmc_init()
1962 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) in tegra_pmc_init_tsense_reset() argument
1966 struct device *dev = pmc->dev; in tegra_pmc_init_tsense_reset()
1970 if (!pmc->soc->has_tsense_reset) in tegra_pmc_init_tsense_reset()
1973 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); in tegra_pmc_init_tsense_reset()
2002 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
2004 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
2008 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); in tegra_pmc_init_tsense_reset()
2026 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); in tegra_pmc_init_tsense_reset()
2028 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
2030 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
2032 dev_info(pmc->dev, "emergency thermal reset enabled\n"); in tegra_pmc_init_tsense_reset()
2040 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinctrl_get_groups_count() local
2042 return pmc->soc->num_io_pads; in tegra_io_pad_pinctrl_get_groups_count()
2048 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); in tegra_io_pad_pinctrl_get_group_name() local
2050 return pmc->soc->io_pads[group].name; in tegra_io_pad_pinctrl_get_group_name()
2058 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinctrl_get_group_pins() local
2060 *pins = &pmc->soc->io_pads[group].id; in tegra_io_pad_pinctrl_get_group_pins()
2078 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinconf_get() local
2083 pad = tegra_io_pad_find(pmc, pin); in tegra_io_pad_pinconf_get()
2089 ret = tegra_io_pad_get_voltage(pmc, pad->id); in tegra_io_pad_pinconf_get()
2097 ret = tegra_io_pad_is_powered(pmc, pad->id); in tegra_io_pad_pinconf_get()
2117 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinconf_set() local
2124 pad = tegra_io_pad_find(pmc, pin); in tegra_io_pad_pinconf_set()
2145 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); in tegra_io_pad_pinconf_set()
2168 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) in tegra_pmc_pinctrl_init() argument
2172 if (!pmc->soc->num_pin_descs) in tegra_pmc_pinctrl_init()
2175 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); in tegra_pmc_pinctrl_init()
2176 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; in tegra_pmc_pinctrl_init()
2177 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; in tegra_pmc_pinctrl_init()
2179 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, in tegra_pmc_pinctrl_init()
2180 pmc); in tegra_pmc_pinctrl_init()
2181 if (IS_ERR(pmc->pctl_dev)) { in tegra_pmc_pinctrl_init()
2182 err = PTR_ERR(pmc->pctl_dev); in tegra_pmc_pinctrl_init()
2183 dev_err(pmc->dev, "failed to register pin controller: %d\n", in tegra_pmc_pinctrl_init()
2196 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_reason_show()
2197 value &= pmc->soc->regs->rst_source_mask; in reset_reason_show()
2198 value >>= pmc->soc->regs->rst_source_shift; in reset_reason_show()
2200 if (WARN_ON(value >= pmc->soc->num_reset_sources)) in reset_reason_show()
2203 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); in reset_reason_show()
2213 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_level_show()
2214 value &= pmc->soc->regs->rst_level_mask; in reset_level_show()
2215 value >>= pmc->soc->regs->rst_level_shift; in reset_level_show()
2217 if (WARN_ON(value >= pmc->soc->num_reset_levels)) in reset_level_show()
2220 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); in reset_level_show()
2225 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) in tegra_pmc_reset_sysfs_init() argument
2227 struct device *dev = pmc->dev; in tegra_pmc_reset_sysfs_init()
2230 if (pmc->soc->reset_sources) { in tegra_pmc_reset_sysfs_init()
2238 if (pmc->soc->reset_levels) { in tegra_pmc_reset_sysfs_init()
2264 struct tegra_pmc *pmc = domain->host_data; in tegra_pmc_irq_alloc() local
2265 const struct tegra_pmc_soc *soc = pmc->soc; in tegra_pmc_irq_alloc()
2285 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2295 spec.fwnode = &pmc->dev->of_node->fwnode; in tegra_pmc_irq_alloc()
2315 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2339 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra210_pmc_irq_set_wake() local
2347 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); in tegra210_pmc_irq_set_wake()
2348 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); in tegra210_pmc_irq_set_wake()
2350 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); in tegra210_pmc_irq_set_wake()
2351 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); in tegra210_pmc_irq_set_wake()
2359 value = tegra_pmc_readl(pmc, offset); in tegra210_pmc_irq_set_wake()
2366 tegra_pmc_writel(pmc, value, offset); in tegra210_pmc_irq_set_wake()
2373 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra210_pmc_irq_set_type() local
2385 value = tegra_pmc_readl(pmc, offset); in tegra210_pmc_irq_set_type()
2406 tegra_pmc_writel(pmc, value, offset); in tegra210_pmc_irq_set_type()
2411 static void tegra186_pmc_set_wake_filters(struct tegra_pmc *pmc) in tegra186_pmc_set_wake_filters() argument
2416 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); in tegra186_pmc_set_wake_filters()
2418 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); in tegra186_pmc_set_wake_filters()
2419 dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value); in tegra186_pmc_set_wake_filters()
2424 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra186_pmc_irq_set_wake() local
2432 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2435 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2442 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2445 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2452 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra186_pmc_irq_set_type() local
2455 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2461 set_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2462 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2468 clear_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2469 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2474 clear_bit(data->hwirq, pmc->wake_type_level_map); in tegra186_pmc_irq_set_type()
2475 set_bit(data->hwirq, pmc->wake_type_dual_edge_map); in tegra186_pmc_irq_set_type()
2482 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2515 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) in tegra_pmc_irq_init() argument
2520 np = of_irq_find_parent(pmc->dev->of_node); in tegra_pmc_irq_init()
2529 pmc->irq.name = dev_name(pmc->dev); in tegra_pmc_irq_init()
2530 pmc->irq.irq_mask = tegra_irq_mask_parent; in tegra_pmc_irq_init()
2531 pmc->irq.irq_unmask = tegra_irq_unmask_parent; in tegra_pmc_irq_init()
2532 pmc->irq.irq_eoi = tegra_irq_eoi_parent; in tegra_pmc_irq_init()
2533 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; in tegra_pmc_irq_init()
2534 pmc->irq.irq_set_type = pmc->soc->irq_set_type; in tegra_pmc_irq_init()
2535 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; in tegra_pmc_irq_init()
2537 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, in tegra_pmc_irq_init()
2538 &tegra_pmc_irq_domain_ops, pmc); in tegra_pmc_irq_init()
2539 if (!pmc->domain) { in tegra_pmc_irq_init()
2540 dev_err(pmc->dev, "failed to allocate domain\n"); in tegra_pmc_irq_init()
2550 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb); in tegra_pmc_clk_notify_cb() local
2555 mutex_lock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2559 pmc->rate = data->new_rate; in tegra_pmc_clk_notify_cb()
2563 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2576 tegra_pmc_readl(pmc, offset); in pmc_clk_fence_udelay()
2586 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; in pmc_clk_mux_get_parent()
2597 val = tegra_pmc_readl(pmc, clk->offs); in pmc_clk_mux_set_parent()
2600 tegra_pmc_writel(pmc, val, clk->offs); in pmc_clk_mux_set_parent()
2611 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); in pmc_clk_is_enabled()
2620 val = tegra_pmc_readl(pmc, offs); in pmc_clk_set_state()
2622 tegra_pmc_writel(pmc, val, offs); in pmc_clk_set_state()
2652 tegra_pmc_clk_out_register(struct tegra_pmc *pmc, in tegra_pmc_clk_out_register() argument
2659 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); in tegra_pmc_clk_out_register()
2682 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; in pmc_clk_gate_is_enabled()
2708 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, in tegra_pmc_clk_gate_register() argument
2715 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); in tegra_pmc_clk_gate_register()
2732 static void tegra_pmc_clock_register(struct tegra_pmc *pmc, in tegra_pmc_clock_register() argument
2740 num_clks = pmc->soc->num_pmc_clks; in tegra_pmc_clock_register()
2741 if (pmc->soc->has_blink_output) in tegra_pmc_clock_register()
2747 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); in tegra_pmc_clock_register()
2751 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, in tegra_pmc_clock_register()
2761 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { in tegra_pmc_clock_register()
2764 data = pmc->soc->pmc_clks_data + i; in tegra_pmc_clock_register()
2766 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); in tegra_pmc_clock_register()
2768 dev_warn(pmc->dev, "unable to register clock %s: %d\n", in tegra_pmc_clock_register()
2775 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2784 if (pmc->soc->has_blink_output) { in tegra_pmc_clock_register()
2785 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); in tegra_pmc_clock_register()
2786 clk = tegra_pmc_clk_gate_register(pmc, in tegra_pmc_clock_register()
2792 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2798 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", in tegra_pmc_clock_register()
2803 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2811 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2822 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", in tegra_pmc_clock_register()
2844 struct tegra_pmc *pmc = context; in tegra_pmc_regmap_readl() local
2846 *value = tegra_pmc_readl(pmc, offset); in tegra_pmc_regmap_readl()
2852 struct tegra_pmc *pmc = context; in tegra_pmc_regmap_writel() local
2854 tegra_pmc_writel(pmc, value, offset); in tegra_pmc_regmap_writel()
2870 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc) in tegra_pmc_regmap_init() argument
2875 if (pmc->soc->has_usb_sleepwalk) { in tegra_pmc_regmap_init()
2876 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); in tegra_pmc_regmap_init()
2879 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); in tegra_pmc_regmap_init()
2889 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; in tegra_pmc_reset_suspend_mode()
2903 if (WARN_ON(!pmc->base || !pmc->soc)) in tegra_pmc_probe()
2906 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2922 pmc->wake = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2923 if (IS_ERR(pmc->wake)) in tegra_pmc_probe()
2924 return PTR_ERR(pmc->wake); in tegra_pmc_probe()
2926 pmc->wake = base; in tegra_pmc_probe()
2931 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2932 if (IS_ERR(pmc->aotag)) in tegra_pmc_probe()
2933 return PTR_ERR(pmc->aotag); in tegra_pmc_probe()
2935 pmc->aotag = base; in tegra_pmc_probe()
2940 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2941 if (IS_ERR(pmc->scratch)) in tegra_pmc_probe()
2942 return PTR_ERR(pmc->scratch); in tegra_pmc_probe()
2944 pmc->scratch = base; in tegra_pmc_probe()
2947 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk"); in tegra_pmc_probe()
2948 if (IS_ERR(pmc->clk)) in tegra_pmc_probe()
2949 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk), in tegra_pmc_probe()
2993 if (pmc->clk) { in tegra_pmc_probe()
2994 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; in tegra_pmc_probe()
2995 err = devm_clk_notifier_register(&pdev->dev, pmc->clk, in tegra_pmc_probe()
2996 &pmc->clk_nb); in tegra_pmc_probe()
3003 pmc->rate = clk_get_rate(pmc->clk); in tegra_pmc_probe()
3006 pmc->dev = &pdev->dev; in tegra_pmc_probe()
3008 err = tegra_pmc_init(pmc); in tegra_pmc_probe()
3014 tegra_pmc_init_tsense_reset(pmc); in tegra_pmc_probe()
3016 tegra_pmc_reset_sysfs_init(pmc); in tegra_pmc_probe()
3018 err = tegra_pmc_pinctrl_init(pmc); in tegra_pmc_probe()
3022 err = tegra_pmc_regmap_init(pmc); in tegra_pmc_probe()
3026 err = tegra_powergate_init(pmc, pdev->dev.of_node); in tegra_pmc_probe()
3030 err = tegra_pmc_irq_init(pmc); in tegra_pmc_probe()
3034 mutex_lock(&pmc->powergates_lock); in tegra_pmc_probe()
3035 iounmap(pmc->base); in tegra_pmc_probe()
3036 pmc->base = base; in tegra_pmc_probe()
3037 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_probe()
3039 tegra_pmc_clock_register(pmc, pdev->dev.of_node); in tegra_pmc_probe()
3040 platform_set_drvdata(pdev, pmc); in tegra_pmc_probe()
3044 if (pmc->soc->set_wake_filters) in tegra_pmc_probe()
3045 pmc->soc->set_wake_filters(pmc); in tegra_pmc_probe()
3064 static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset) in wke_32kwritel() argument
3066 writel(value, pmc->wake + offset); in wke_32kwritel()
3070 static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level) in wke_write_wake_level() argument
3075 value = readl(pmc->wake + offset); in wke_write_wake_level()
3081 writel(value, pmc->wake + offset); in wke_write_wake_level()
3084 static void wke_write_wake_levels(struct tegra_pmc *pmc) in wke_write_wake_levels() argument
3088 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_write_wake_levels()
3089 wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map)); in wke_write_wake_levels()
3092 static void wke_clear_sw_wake_status(struct tegra_pmc *pmc) in wke_clear_sw_wake_status() argument
3094 wke_32kwritel(pmc, 1, WAKE_AOWAKE_SW_STATUS_W_0); in wke_clear_sw_wake_status()
3097 static void wke_read_sw_wake_status(struct tegra_pmc *pmc) in wke_read_sw_wake_status() argument
3102 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_read_sw_wake_status()
3103 wke_write_wake_level(pmc, i, 0); in wke_read_sw_wake_status()
3105 wke_clear_sw_wake_status(pmc); in wke_read_sw_wake_status()
3107 wke_32kwritel(pmc, 1, WAKE_LATCH_SW); in wke_read_sw_wake_status()
3115 for (i = 0; i < pmc->soc->max_wake_events; i++) in wke_read_sw_wake_status()
3116 wke_write_wake_level(pmc, i, 1); in wke_read_sw_wake_status()
3125 wke_32kwritel(pmc, 0, WAKE_LATCH_SW); in wke_read_sw_wake_status()
3127 bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events); in wke_read_sw_wake_status()
3129 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in wke_read_sw_wake_status()
3130 status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i)); in wke_read_sw_wake_status()
3133 set_bit(wake + (i * 32), pmc->wake_sw_status_map); in wke_read_sw_wake_status()
3137 static void wke_clear_wake_status(struct tegra_pmc *pmc) in wke_clear_wake_status() argument
3143 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in wke_clear_wake_status()
3144 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); in wke_clear_wake_status()
3145 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; in wke_clear_wake_status()
3148 wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W((i * 32) + wake)); in wke_clear_wake_status()
3153 static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int index, in tegra186_pmc_process_wake_events() argument
3158 dev_dbg(pmc->dev, "Wake[%d:%d] status=%#lx\n", (index * 32) + 31, index * 32, status); in tegra186_pmc_process_wake_events()
3165 irq = irq_find_mapping(pmc->domain, hwirq); in tegra186_pmc_process_wake_events()
3169 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq); in tegra186_pmc_process_wake_events()
3173 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name); in tegra186_pmc_process_wake_events()
3183 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { in tegra186_pmc_wake_syscore_resume()
3184 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); in tegra186_pmc_wake_syscore_resume()
3185 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; in tegra186_pmc_wake_syscore_resume()
3187 tegra186_pmc_process_wake_events(pmc, i, status); in tegra186_pmc_wake_syscore_resume()
3193 wke_read_sw_wake_status(pmc); in tegra186_pmc_wake_syscore_suspend()
3198 bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map, in tegra186_pmc_wake_syscore_suspend()
3199 pmc->wake_sw_status_map, pmc->soc->max_wake_events); in tegra186_pmc_wake_syscore_suspend()
3200 bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map, in tegra186_pmc_wake_syscore_suspend()
3201 pmc->wake_type_level_map, pmc->soc->max_wake_events); in tegra186_pmc_wake_syscore_suspend()
3204 wke_clear_wake_status(pmc); in tegra186_pmc_wake_syscore_suspend()
3205 wke_write_wake_levels(pmc); in tegra186_pmc_wake_syscore_suspend()
3213 struct tegra_pmc *pmc = dev_get_drvdata(dev); in tegra_pmc_suspend() local
3215 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); in tegra_pmc_suspend()
3222 struct tegra_pmc *pmc = dev_get_drvdata(dev); in tegra_pmc_resume() local
3224 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); in tegra_pmc_resume()
3252 static void tegra20_pmc_init(struct tegra_pmc *pmc) in tegra20_pmc_init() argument
3257 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
3259 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
3261 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
3263 if (pmc->sysclkreq_high) in tegra20_pmc_init()
3268 if (pmc->corereq_high) in tegra20_pmc_init()
3274 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
3277 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
3279 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
3282 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { in tegra20_pmc_init()
3283 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); in tegra20_pmc_init()
3284 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); in tegra20_pmc_init()
3285 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); in tegra20_pmc_init()
3286 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), in tegra20_pmc_init()
3288 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); in tegra20_pmc_init()
3292 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, in tegra20_pmc_setup_irq_polarity() argument
3298 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_setup_irq_polarity()
3305 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_setup_irq_polarity()
3853 static void tegra186_pmc_init(struct tegra_pmc *pmc) in tegra186_pmc_init() argument
3855 pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend; in tegra186_pmc_init()
3856 pmc->syscore.resume = tegra186_pmc_wake_syscore_resume; in tegra186_pmc_init()
3858 register_syscore_ops(&pmc->syscore); in tegra186_pmc_init()
3861 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, in tegra186_pmc_setup_irq_polarity() argument
3872 dev_err(pmc->dev, "failed to find PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3880 dev_err(pmc->dev, "failed to map PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
4294 if (!pmc->soc->supports_core_domain) in tegra_pmc_sync_state()
4302 if (!pmc->core_domain_registered) in tegra_pmc_sync_state()
4305 pmc->core_domain_state_synced = true; in tegra_pmc_sync_state()
4308 mutex_lock(&pmc->powergates_lock); in tegra_pmc_sync_state()
4310 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_sync_state()
4330 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) in tegra_pmc_detect_tz_only() argument
4334 saved = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4341 writel(value, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4342 value = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4351 writel(saved, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4368 mutex_init(&pmc->powergates_lock); in tegra_pmc_early_init()
4409 pmc->base = ioremap(regs.start, resource_size(®s)); in tegra_pmc_early_init()
4410 if (!pmc->base) { in tegra_pmc_early_init()
4417 pmc->soc = match->data; in tegra_pmc_early_init()
4419 if (pmc->soc->maybe_tz_only) in tegra_pmc_early_init()
4420 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); in tegra_pmc_early_init()
4423 for (i = 0; i < pmc->soc->num_powergates; i++) in tegra_pmc_early_init()
4424 if (pmc->soc->powergates[i]) in tegra_pmc_early_init()
4425 set_bit(i, pmc->powergates_available); in tegra_pmc_early_init()
4433 pmc->soc->setup_irq_polarity(pmc, np, invert); in tegra_pmc_early_init()