Lines Matching refs:value
505 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, in tegra_pmc_writel() argument
512 value, 0, 0, 0, 0, &res); in tegra_pmc_writel()
522 writel(value, pmc->base + offset); in tegra_pmc_writel()
534 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, in tegra_pmc_scratch_writel() argument
538 tegra_pmc_writel(pmc, value, offset); in tegra_pmc_scratch_writel()
540 writel(value, pmc->scratch + offset); in tegra_pmc_scratch_writel()
1103 u32 value; in tegra_pmc_program_reboot_reason() local
1105 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); in tegra_pmc_program_reboot_reason()
1106 value &= ~PMC_SCRATCH0_MODE_MASK; in tegra_pmc_program_reboot_reason()
1110 value |= PMC_SCRATCH0_MODE_RECOVERY; in tegra_pmc_program_reboot_reason()
1113 value |= PMC_SCRATCH0_MODE_BOOTLOADER; in tegra_pmc_program_reboot_reason()
1116 value |= PMC_SCRATCH0_MODE_RCM; in tegra_pmc_program_reboot_reason()
1119 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); in tegra_pmc_program_reboot_reason()
1137 u32 value; in tegra_pmc_restart() local
1140 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra_pmc_restart()
1141 value |= PMC_CNTRL_MAIN_RST; in tegra_pmc_restart()
1142 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra_pmc_restart()
1557 unsigned long rate, value; in tegra_io_pad_prepare() local
1576 value = DIV_ROUND_UP(1000000000, rate); in tegra_io_pad_prepare()
1577 value = DIV_ROUND_UP(200, value); in tegra_io_pad_prepare()
1578 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); in tegra_io_pad_prepare()
1587 u32 value; in tegra_io_pad_poll() local
1592 value = tegra_pmc_readl(pmc, offset); in tegra_io_pad_poll()
1593 if ((value & mask) == val) in tegra_io_pad_poll()
1698 u32 mask, value; in tegra_io_pad_is_powered() local
1712 value = tegra_pmc_readl(pmc, status); in tegra_io_pad_is_powered()
1714 return !(value & mask); in tegra_io_pad_is_powered()
1721 u32 value; in tegra_io_pad_set_voltage() local
1733 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); in tegra_io_pad_set_voltage()
1736 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1738 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1740 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); in tegra_io_pad_set_voltage()
1743 value = tegra_pmc_readl(pmc, PMC_PWR_DET); in tegra_io_pad_set_voltage()
1744 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1745 tegra_pmc_writel(pmc, value, PMC_PWR_DET); in tegra_io_pad_set_voltage()
1748 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); in tegra_io_pad_set_voltage()
1751 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1753 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1755 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); in tegra_io_pad_set_voltage()
1768 u32 value; in tegra_io_pad_get_voltage() local
1778 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); in tegra_io_pad_get_voltage()
1780 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); in tegra_io_pad_get_voltage()
1782 if ((value & BIT(pad->voltage)) == 0) in tegra_io_pad_get_voltage()
1830 u32 value; in tegra_pmc_enter_suspend_mode() local
1856 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra_pmc_enter_suspend_mode()
1857 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; in tegra_pmc_enter_suspend_mode()
1858 value |= PMC_CNTRL_CPU_PWRREQ_OE; in tegra_pmc_enter_suspend_mode()
1859 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra_pmc_enter_suspend_mode()
1865 u32 value, values[2]; in tegra_pmc_parse_dt() local
1867 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { in tegra_pmc_parse_dt()
1870 switch (value) { in tegra_pmc_parse_dt()
1891 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) in tegra_pmc_parse_dt()
1894 pmc->cpu_good_time = value; in tegra_pmc_parse_dt()
1896 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1899 pmc->cpu_off_time = value; in tegra_pmc_parse_dt()
1908 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1911 pmc->core_off_time = value; in tegra_pmc_parse_dt()
1968 u32 value, checksum; in tegra_pmc_init_tsense_reset() local
2002 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
2003 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; in tegra_pmc_init_tsense_reset()
2004 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
2006 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | in tegra_pmc_init_tsense_reset()
2008 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); in tegra_pmc_init_tsense_reset()
2010 value = PMC_SCRATCH55_RESET_TEGRA; in tegra_pmc_init_tsense_reset()
2011 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; in tegra_pmc_init_tsense_reset()
2012 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; in tegra_pmc_init_tsense_reset()
2013 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; in tegra_pmc_init_tsense_reset()
2019 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) in tegra_pmc_init_tsense_reset()
2020 + ((value >> 24) & 0xff); in tegra_pmc_init_tsense_reset()
2024 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; in tegra_pmc_init_tsense_reset()
2026 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); in tegra_pmc_init_tsense_reset()
2028 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
2029 value |= PMC_SENSOR_CTRL_ENABLE_RST; in tegra_pmc_init_tsense_reset()
2030 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
2194 u32 value; in reset_reason_show() local
2196 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_reason_show()
2197 value &= pmc->soc->regs->rst_source_mask; in reset_reason_show()
2198 value >>= pmc->soc->regs->rst_source_shift; in reset_reason_show()
2200 if (WARN_ON(value >= pmc->soc->num_reset_sources)) in reset_reason_show()
2203 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); in reset_reason_show()
2211 u32 value; in reset_level_show() local
2213 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_level_show()
2214 value &= pmc->soc->regs->rst_level_mask; in reset_level_show()
2215 value >>= pmc->soc->regs->rst_level_shift; in reset_level_show()
2217 if (WARN_ON(value >= pmc->soc->num_reset_levels)) in reset_level_show()
2220 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); in reset_level_show()
2341 u32 value; in tegra210_pmc_irq_set_wake() local
2359 value = tegra_pmc_readl(pmc, offset); in tegra210_pmc_irq_set_wake()
2362 value |= BIT(bit); in tegra210_pmc_irq_set_wake()
2364 value &= ~BIT(bit); in tegra210_pmc_irq_set_wake()
2366 tegra_pmc_writel(pmc, value, offset); in tegra210_pmc_irq_set_wake()
2375 u32 value; in tegra210_pmc_irq_set_type() local
2385 value = tegra_pmc_readl(pmc, offset); in tegra210_pmc_irq_set_type()
2390 value |= BIT(bit); in tegra210_pmc_irq_set_type()
2395 value &= ~BIT(bit); in tegra210_pmc_irq_set_type()
2399 value ^= BIT(bit); in tegra210_pmc_irq_set_type()
2406 tegra_pmc_writel(pmc, value, offset); in tegra210_pmc_irq_set_type()
2413 u32 value; in tegra186_pmc_set_wake_filters() local
2416 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); in tegra186_pmc_set_wake_filters()
2417 value |= WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN; in tegra186_pmc_set_wake_filters()
2418 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); in tegra186_pmc_set_wake_filters()
2419 dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value); in tegra186_pmc_set_wake_filters()
2426 u32 value; in tegra186_pmc_irq_set_wake() local
2435 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2438 value &= ~(1 << bit); in tegra186_pmc_irq_set_wake()
2440 value |= 1 << bit; in tegra186_pmc_irq_set_wake()
2442 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2453 u32 value; in tegra186_pmc_irq_set_type() local
2455 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2460 value |= WAKE_AOWAKE_CNTRL_LEVEL; in tegra186_pmc_irq_set_type()
2467 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; in tegra186_pmc_irq_set_type()
2473 value ^= WAKE_AOWAKE_CNTRL_LEVEL; in tegra186_pmc_irq_set_type()
2482 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2842 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value) in tegra_pmc_regmap_readl() argument
2846 *value = tegra_pmc_readl(pmc, offset); in tegra_pmc_regmap_readl()
2850 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value) in tegra_pmc_regmap_writel() argument
2854 tegra_pmc_writel(pmc, value, offset); in tegra_pmc_regmap_writel()
3064 static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset) in wke_32kwritel() argument
3066 writel(value, pmc->wake + offset); in wke_32kwritel()
3073 u32 value; in wke_write_wake_level() local
3075 value = readl(pmc->wake + offset); in wke_write_wake_level()
3077 value |= WAKE_AOWAKE_CNTRL_LEVEL; in wke_write_wake_level()
3079 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; in wke_write_wake_level()
3081 writel(value, pmc->wake + offset); in wke_write_wake_level()
3254 u32 value, osc, pmu, off; in tegra20_pmc_init() local
3257 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
3258 value |= PMC_CNTRL_CPU_PWRREQ_OE; in tegra20_pmc_init()
3259 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
3261 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
3264 value &= ~PMC_CNTRL_SYSCLK_POLARITY; in tegra20_pmc_init()
3266 value |= PMC_CNTRL_SYSCLK_POLARITY; in tegra20_pmc_init()
3269 value &= ~PMC_CNTRL_PWRREQ_POLARITY; in tegra20_pmc_init()
3271 value |= PMC_CNTRL_PWRREQ_POLARITY; in tegra20_pmc_init()
3274 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
3277 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
3278 value |= PMC_CNTRL_SYSCLK_OE; in tegra20_pmc_init()
3279 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
3296 u32 value; in tegra20_pmc_setup_irq_polarity() local
3298 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_setup_irq_polarity()
3301 value |= PMC_CNTRL_INTR_POLARITY; in tegra20_pmc_setup_irq_polarity()
3303 value &= ~PMC_CNTRL_INTR_POLARITY; in tegra20_pmc_setup_irq_polarity()
3305 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_setup_irq_polarity()
3867 u32 value; in tegra186_pmc_setup_irq_polarity() local
3884 value = readl(wake + WAKE_AOWAKE_CTRL); in tegra186_pmc_setup_irq_polarity()
3887 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; in tegra186_pmc_setup_irq_polarity()
3889 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; in tegra186_pmc_setup_irq_polarity()
3891 writel(value, wake + WAKE_AOWAKE_CTRL); in tegra186_pmc_setup_irq_polarity()
4332 u32 value, saved; in tegra_pmc_detect_tz_only() local
4335 value = saved ^ 0xffffffff; in tegra_pmc_detect_tz_only()
4337 if (value == 0xffffffff) in tegra_pmc_detect_tz_only()
4338 value = 0xdeadbeef; in tegra_pmc_detect_tz_only()
4341 writel(value, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4342 value = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
4345 if (value == 0) { in tegra_pmc_detect_tz_only()