1 // SPDX-License-Identifier: GPL-2.0-only
7  * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
74 	unsigned int reg;  in flowctrl_cpu_suspend_enter()  local
77 	reg = flowctrl_read_cpu_csr(cpuid);  in flowctrl_cpu_suspend_enter()
81 		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;  in flowctrl_cpu_suspend_enter()
83 		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;  in flowctrl_cpu_suspend_enter()
84 		/* pwr gating on wfe */  in flowctrl_cpu_suspend_enter()
85 		reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;  in flowctrl_cpu_suspend_enter()
91 		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;  in flowctrl_cpu_suspend_enter()
93 		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;  in flowctrl_cpu_suspend_enter()
99 			 * power-gating (like memory running off PLLP),  in flowctrl_cpu_suspend_enter()
103 			 * while wfe for the power-gating, just like it  in flowctrl_cpu_suspend_enter()
106 			reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;  in flowctrl_cpu_suspend_enter()
108 			/* pwr gating on wfi */  in flowctrl_cpu_suspend_enter()
109 			reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;  in flowctrl_cpu_suspend_enter()
113 	reg |= FLOW_CTRL_CSR_INTR_FLAG;			/* clear intr flag */  in flowctrl_cpu_suspend_enter()
114 	reg |= FLOW_CTRL_CSR_EVENT_FLAG;		/* clear event flag */  in flowctrl_cpu_suspend_enter()
115 	reg |= FLOW_CTRL_CSR_ENABLE;			/* pwr gating */  in flowctrl_cpu_suspend_enter()
116 	flowctrl_write_cpu_csr(cpuid, reg);  in flowctrl_cpu_suspend_enter()
121 		reg = flowctrl_read_cpu_csr(i);  in flowctrl_cpu_suspend_enter()
122 		reg |= FLOW_CTRL_CSR_EVENT_FLAG;  in flowctrl_cpu_suspend_enter()
123 		reg |= FLOW_CTRL_CSR_INTR_FLAG;  in flowctrl_cpu_suspend_enter()
124 		flowctrl_write_cpu_csr(i, reg);  in flowctrl_cpu_suspend_enter()
130 	unsigned int reg;  in flowctrl_cpu_suspend_exit()  local
133 	reg = flowctrl_read_cpu_csr(cpuid);  in flowctrl_cpu_suspend_exit()
137 		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;  in flowctrl_cpu_suspend_exit()
139 		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;  in flowctrl_cpu_suspend_exit()
145 		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;  in flowctrl_cpu_suspend_exit()
147 		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;  in flowctrl_cpu_suspend_exit()
150 	reg &= ~FLOW_CTRL_CSR_ENABLE;			/* clear enable */  in flowctrl_cpu_suspend_exit()
151 	reg |= FLOW_CTRL_CSR_INTR_FLAG;			/* clear intr */  in flowctrl_cpu_suspend_exit()
152 	reg |= FLOW_CTRL_CSR_EVENT_FLAG;		/* clear event */  in flowctrl_cpu_suspend_exit()
153 	flowctrl_write_cpu_csr(cpuid, reg);  in flowctrl_cpu_suspend_exit()
170 	{ .compatible = "nvidia,tegra210-flowctrl" },
171 	{ .compatible = "nvidia,tegra124-flowctrl" },
172 	{ .compatible = "nvidia,tegra114-flowctrl" },
173 	{ .compatible = "nvidia,tegra30-flowctrl" },
174 	{ .compatible = "nvidia,tegra20-flowctrl" },
180 		.name = "tegra-flowctrl",
200 			return -ENXIO;  in tegra_flowctrl_init()
205 		 * Hardcoded fallback for 32-bit Tegra  in tegra_flowctrl_init()
222 		return -ENXIO;  in tegra_flowctrl_init()