35 /* svs bank 1-line software id */
41 /* svs bank 2-line type */
45 /* svs bank mode support */
51 /* svs bank volt flags */
58 /* svs bank register fields and common configuration */
131 /* svs bank related setting */
178  * enum svsb_phase - svs bank phase enumeration
179  * @SVSB_PHASE_ERROR: svs bank encounters unexpected condition
180  * @SVSB_PHASE_INIT01: svs bank basic init for data calibration
181  * @SVSB_PHASE_INIT02: svs bank can provide voltages to opp table
182  * @SVSB_PHASE_MON: svs bank can provide voltages with thermal effect
183  * @SVSB_PHASE_MAX: total number of svs bank phase (debug purpose)
185  * Each svs bank has its own independent phase and we enable each svs bank by
186  * running their phase orderly. However, when svs bank encounters unexpected
187  * condition, it will fire an irq (PHASE_ERROR) to inform svs software.
189  * svs bank general phase-enabled order:
316  * struct svs_platform - svs platform control
317  * @base: svs platform register base
318  * @dev: svs platform device
319  * @main_clk: main clock for svs bank
320  * @pbank: svs bank pointer needing to be protected by spin_lock section
321  * @banks: svs banks that svs platform supports
322  * @rst: svs platform reset control
323  * @efuse_max: total number of svs efuse
325  * @regs: svs platform registers map
326  * @bank_max: total number of svs banks
327  * @efuse: svs efuse data received from NVMEM framework
355  * struct svs_bank - svs bank representation
395  * @cpu_id: cpu core id for SVS CPU bank use only
402  * @bts: svs efuse data
403  * @mts: svs efuse data
404  * @bdes: svs efuse data
405  * @mdes: svs efuse data
406  * @mtdes: svs efuse data
407  * @dcbdet: svs efuse data
408  * @dcmdet: svs efuse data
412  * Svs bank will generate suitalbe voltages by below general math equation
787 	const char *d = "/sys/kernel/debug/svs";  in svs_create_debug_cmds()
804 	svs_dir = debugfs_create_dir("svs", NULL);  in svs_create_debug_cmds()
1262 		/* Find out which svs bank fires interrupt */  in svs_isr()
1307 	 /* Svs bank init01 preparation - power enable */  in svs_init01()
1341 	 * Svs bank init01 preparation - vboot voltage adjustment  in svs_init01()
1342 	 * Sometimes two svs banks use the same buck. Therefore,  in svs_init01()
1343 	 * we have to set each svs bank to target voltage(vboot) first.  in svs_init01()
1389 	/* Svs bank init01 begins */  in svs_init01()
1590 		dev_err(svsp->dev, "cannot enable main_clk, disable svs\n");  in svs_resume()
1762 	/* Svs efuse parsing */  in svs_mt8192_efuse_parsing()
1830 	/* Svs efuse parsing */  in svs_mt8183_efuse_parsing()
2053 				     "cannot get svs reset control\n");  in svs_mt8192_platform_probe()
2281 	.name = "mt8192-svs",
2290 	.name = "mt8183-svs",
2300 		.compatible = "mediatek,mt8192-svs",
2303 		.compatible = "mediatek,mt8183-svs",
2332 	ret = svs_get_efuse_data(svsp, "svs-calibration-data",  in svs_probe()
2347 		dev_err(svsp->dev, "svs bank resource setup fail: %d\n", ret);  in svs_probe()
2373 		dev_err(svsp->dev, "cannot find svs register base\n");  in svs_probe()
2388 		dev_err(svsp->dev, "svs start fail: %d\n", ret);  in svs_probe()
2395 		dev_err(svsp->dev, "svs create debug cmds fail: %d\n", ret);  in svs_probe()
2424 		.name		= "mtk-svs",
2433 MODULE_DESCRIPTION("MediaTek SVS driver");