38 	struct qe_gpio_chip *qe_gc =  in qe_gpio_save_regs()  local
42 	qe_gc->cpdata = ioread32be(&regs->cpdata);  in qe_gpio_save_regs()
43 	qe_gc->saved_regs.cpdata = qe_gc->cpdata;  in qe_gpio_save_regs()
44 	qe_gc->saved_regs.cpdir1 = ioread32be(&regs->cpdir1);  in qe_gpio_save_regs()
45 	qe_gc->saved_regs.cpdir2 = ioread32be(&regs->cpdir2);  in qe_gpio_save_regs()
46 	qe_gc->saved_regs.cppar1 = ioread32be(&regs->cppar1);  in qe_gpio_save_regs()
47 	qe_gc->saved_regs.cppar2 = ioread32be(&regs->cppar2);  in qe_gpio_save_regs()
48 	qe_gc->saved_regs.cpodr = ioread32be(&regs->cpodr);  in qe_gpio_save_regs()
63 	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);  in qe_gpio_set()  local
68 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_gpio_set()
71 		qe_gc->cpdata |= pin_mask;  in qe_gpio_set()
73 		qe_gc->cpdata &= ~pin_mask;  in qe_gpio_set()
75 	iowrite32be(qe_gc->cpdata, &regs->cpdata);  in qe_gpio_set()
77 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_gpio_set()
84 	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);  in qe_gpio_set_multiple()  local
89 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_gpio_set_multiple()
96 				qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i));  in qe_gpio_set_multiple()
98 				qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i));  in qe_gpio_set_multiple()
102 	iowrite32be(qe_gc->cpdata, &regs->cpdata);  in qe_gpio_set_multiple()
104 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_gpio_set_multiple()
110 	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);  in qe_gpio_dir_in()  local
113 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_gpio_dir_in()
117 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_gpio_dir_in()
125 	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);  in qe_gpio_dir_out()  local
130 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_gpio_dir_out()
134 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_gpio_dir_out()
237 	struct qe_gpio_chip *qe_gc = qe_pin->controller;  in qe_pin_set_dedicated()  local
238 	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;  in qe_pin_set_dedicated()
239 	struct qe_pio_regs *sregs = &qe_gc->saved_regs;  in qe_pin_set_dedicated()
246 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_pin_set_dedicated()
261 		qe_gc->cpdata |= mask1;  in qe_pin_set_dedicated()
263 		qe_gc->cpdata &= ~mask1;  in qe_pin_set_dedicated()
265 	iowrite32be(qe_gc->cpdata, &regs->cpdata);  in qe_pin_set_dedicated()
268 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_pin_set_dedicated()
281 	struct qe_gpio_chip *qe_gc = qe_pin->controller;  in qe_pin_set_gpio()  local
282 	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;  in qe_pin_set_gpio()
285 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_pin_set_gpio()
290 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_pin_set_gpio()
300 		struct qe_gpio_chip *qe_gc;  in qe_add_gpiochips()  local
304 		qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);  in qe_add_gpiochips()
305 		if (!qe_gc) {  in qe_add_gpiochips()
310 		spin_lock_init(&qe_gc->lock);  in qe_add_gpiochips()
312 		mm_gc = &qe_gc->mm_gc;  in qe_add_gpiochips()
323 		ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);  in qe_add_gpiochips()
330 		kfree(qe_gc);  in qe_add_gpiochips()