Lines Matching +full:0 +full:x0bf8
41 #define REG_QCSP_LIO_CFG(n) (0x0000 + ((n) * 0x10))
42 #define REG_QCSP_IO_CFG(n) (0x0004 + ((n) * 0x10))
43 #define REG_QCSP_DD_CFG(n) (0x000c + ((n) * 0x10))
44 #define REG_DD_CFG 0x0200
45 #define REG_DCP_CFG(n) (0x0300 + ((n) * 0x10))
46 #define REG_DCP_DD_CFG(n) (0x0304 + ((n) * 0x10))
47 #define REG_DCP_DLM_AVG(n) (0x030c + ((n) * 0x10))
48 #define REG_PFDR_FPC 0x0400
49 #define REG_PFDR_FP_HEAD 0x0404
50 #define REG_PFDR_FP_TAIL 0x0408
51 #define REG_PFDR_FP_LWIT 0x0410
52 #define REG_PFDR_CFG 0x0414
53 #define REG_SFDR_CFG 0x0500
54 #define REG_SFDR_IN_USE 0x0504
55 #define REG_WQ_CS_CFG(n) (0x0600 + ((n) * 0x04))
56 #define REG_WQ_DEF_ENC_WQID 0x0630
57 #define REG_WQ_SC_DD_CFG(n) (0x640 + ((n) * 0x04))
58 #define REG_WQ_PC_DD_CFG(n) (0x680 + ((n) * 0x04))
59 #define REG_WQ_DC0_DD_CFG(n) (0x6c0 + ((n) * 0x04))
60 #define REG_WQ_DC1_DD_CFG(n) (0x700 + ((n) * 0x04))
61 #define REG_WQ_DCn_DD_CFG(n) (0x6c0 + ((n) * 0x40)) /* n=2,3 */
62 #define REG_CM_CFG 0x0800
63 #define REG_ECSR 0x0a00
64 #define REG_ECIR 0x0a04
65 #define REG_EADR 0x0a08
66 #define REG_ECIR2 0x0a0c
67 #define REG_EDATA(n) (0x0a10 + ((n) * 0x04))
68 #define REG_SBEC(n) (0x0a80 + ((n) * 0x04))
69 #define REG_MCR 0x0b00
70 #define REG_MCP(n) (0x0b04 + ((n) * 0x04))
71 #define REG_MISC_CFG 0x0be0
72 #define REG_HID_CFG 0x0bf0
73 #define REG_IDLE_STAT 0x0bf4
74 #define REG_IP_REV_1 0x0bf8
75 #define REG_IP_REV_2 0x0bfc
76 #define REG_FQD_BARE 0x0c00
77 #define REG_PFDR_BARE 0x0c20
78 #define REG_offset_BAR 0x0004 /* relative to REG_[FQD|PFDR]_BARE */
79 #define REG_offset_AR 0x0010 /* relative to REG_[FQD|PFDR]_BARE */
80 #define REG_QCSP_BARE 0x0c80
81 #define REG_QCSP_BAR 0x0c84
82 #define REG_CI_SCHED_CFG 0x0d00
83 #define REG_SRCIDR 0x0d04
84 #define REG_LIODNR 0x0d08
85 #define REG_CI_RLM_AVG 0x0d14
86 #define REG_ERR_ISR 0x0e00
87 #define REG_ERR_IER 0x0e04
88 #define REG_REV3_QCSP_LIO_CFG(n) (0x1000 + ((n) * 0x10))
89 #define REG_REV3_QCSP_IO_CFG(n) (0x1004 + ((n) * 0x10))
90 #define REG_REV3_QCSP_DD_CFG(n) (0x100c + ((n) * 0x10))
93 #define MCR_INIT_PFDR 0x01000000
95 #define MCR_rslt_idle(r) (!(r) || ((r) >= 0xf0))
96 #define MCR_rslt_ok(r) ((r) == 0xf0)
97 #define MCR_rslt_eaccess(r) ((r) == 0xf8)
98 #define MCR_rslt_inval(r) ((r) == 0xff)
113 qm_wq_portal = 0,
130 #define QM_EIRQ_CIDE 0x20000000 /* Corenet Initiator Data Error */
131 #define QM_EIRQ_CTDE 0x10000000 /* Corenet Target Data Error */
132 #define QM_EIRQ_CITT 0x08000000 /* Corenet Invalid Target Transaction */
133 #define QM_EIRQ_PLWI 0x04000000 /* PFDR Low Watermark */
134 #define QM_EIRQ_MBEI 0x02000000 /* Multi-bit ECC Error */
135 #define QM_EIRQ_SBEI 0x01000000 /* Single-bit ECC Error */
136 #define QM_EIRQ_PEBI 0x00800000 /* PFDR Enqueues Blocked Interrupt */
137 #define QM_EIRQ_IFSI 0x00020000 /* Invalid FQ Flow Control State */
138 #define QM_EIRQ_ICVI 0x00010000 /* Invalid Command Verb */
139 #define QM_EIRQ_IDDI 0x00000800 /* Invalid Dequeue (Direct-connect) */
140 #define QM_EIRQ_IDFI 0x00000400 /* Invalid Dequeue FQ */
141 #define QM_EIRQ_IDSI 0x00000200 /* Invalid Dequeue Source */
142 #define QM_EIRQ_IDQI 0x00000100 /* Invalid Dequeue Queue */
143 #define QM_EIRQ_IECE 0x00000010 /* Invalid Enqueue Configuration */
144 #define QM_EIRQ_IEOI 0x00000008 /* Invalid Enqueue Overflow */
145 #define QM_EIRQ_IESI 0x00000004 /* Invalid Enqueue State */
146 #define QM_EIRQ_IECI 0x00000002 /* Invalid Enqueue Channel */
147 #define QM_EIRQ_IEQI 0x00000001 /* Invalid Enqueue Queue */
158 u32 info; /* res[30-31], ptyp[29], pnum[24-28], fqid[0-23] */
168 return (p->info >> 24) & 0x1f; in qm_ecir_get_pnum()
177 u32 info; /* ptyp[31], res[10-30], pnum[0-9] */
191 u32 info; /* memid[24-27], eadr[0-11] */
192 /* v3: memid[24-28], eadr[0-15] */
197 return (p->info >> 24) & 0xf; in qm_eadr_get_memid()
207 return (p->info >> 24) & 0x1f; in qm_eadr_v3_get_memid()
249 { 0x01FF, 24, "FQD cache tag memory 0" },
250 { 0x01FF, 24, "FQD cache tag memory 1" },
251 { 0x01FF, 24, "FQD cache tag memory 2" },
252 { 0x01FF, 24, "FQD cache tag memory 3" },
253 { 0x0FFF, 512, "FQD cache memory" },
254 { 0x07FF, 128, "SFDR memory" },
255 { 0x01FF, 72, "WQ context memory" },
256 { 0x00FF, 240, "CGR memory" },
257 { 0x00FF, 302, "Internal Order Restoration List memory" },
258 { 0x01FF, 256, "SW portal ring memory" },
295 qm_dc_portal_fman0 = 0,
303 if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) in qm_set_dc()
305 (ed ? 0x1000 : 0) | (sernd & 0x3ff)); in qm_set_dc()
308 (ed ? 0x100 : 0) | (sernd & 0x1f)); in qm_set_dc()
315 qm_ccsr_out(REG_WQ_CS_CFG(wq_class), ((cs_elev & 0xff) << 24) | in qm_set_wq_scheduling()
316 ((csw2 & 0x7) << 20) | ((csw3 & 0x7) << 16) | in qm_set_wq_scheduling()
317 ((csw4 & 0x7) << 12) | ((csw5 & 0x7) << 8) | in qm_set_wq_scheduling()
318 ((csw6 & 0x7) << 4) | (csw7 & 0x7)); in qm_set_wq_scheduling()
323 qm_ccsr_out(REG_HID_CFG, 0); in qm_set_hid()
339 *major = (v >> 8) & 0xff; in qm_get_version()
340 *minor = v & 0xff; in qm_get_version()
363 pr_err("Attempted to reinitialize QMan with different BAR, got 0x%llx read BARE=0x%x BAR=0x%x\n", in qm_set_memory()
377 memset(ptr, 0, size); in qm_set_memory()
392 return 0; in qm_set_memory()
397 qm_ccsr_out(REG_PFDR_FP_LWIT, th & 0xffffff); in qm_set_pfdr_threshold()
403 qm_ccsr_out(REG_SFDR_CFG, th & 0x3ff); in qm_set_sfdr_threshold()
418 qm_ccsr_out(REG_MCP(0), pfdr_start); in qm_init_pfdr()
432 return 0; in qm_init_pfdr()
464 memset_io(tmpp, 0, sz); in zero_priv_mem()
469 return 0; in zero_priv_mem()
478 return 0; in qman_fqd()
489 return 0; in qman_pfdr()
502 u32 i, j, mask = 0xffffffff; in log_edata_bits()
511 dev_warn(dev, " 0x%08x\n", qm_ccsr_in(REG_EDATA(j)) & mask); in log_edata_bits()
514 dev_warn(dev, " 0x%08x\n", qm_ccsr_in(REG_EDATA(j))); in log_edata_bits()
526 if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) { in log_additional_error_info()
536 dev_warn(dev, "ErrInt: ecir.fqid 0x%x\n", in log_additional_error_info()
542 dev_warn(dev, "ErrInt: EADR Memory: %s, 0x%x\n", in log_additional_error_info()
555 dev_warn(dev, "ErrInt: ecir.fqid 0x%x\n", in log_additional_error_info()
561 dev_warn(dev, "ErrInt: EADR Memory: %s, 0x%x\n", in log_additional_error_info()
583 for (i = 0; i < ARRAY_SIZE(qman_hwerr_txts); i++) { in qman_isr()
594 dev_dbg(dev, "Disabling error 0x%x\n", in qman_isr()
612 if (err < 0) in qman_init_ccsr()
616 if (err < 0) in qman_init_ccsr()
619 if (err == 0) { in qman_init_ccsr()
635 qm_set_wq_scheduling(i, 0, 0, 0, 0, 0, 0, 0); in qman_init_ccsr()
637 qm_set_dc(qm_dc_portal_fman0, 1, 0); in qman_init_ccsr()
638 qm_set_dc(qm_dc_portal_fman1, 1, 0); in qman_init_ccsr()
639 return 0; in qman_init_ccsr()
642 #define LIO_CFG_LIODN_MASK 0x0fff0000
650 if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) in __qman_liodn_fixup()
660 if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) in __qman_liodn_fixup()
666 #define IO_CFG_SDEST_MASK 0x00ff0000
672 if ((qman_ip_rev & 0xFF00) >= QMAN_REV30) { in qman_set_sdest()
721 for (i = 0; i < cgrid_num; i++) in qman_resource_init()
731 return 0; in qman_resource_init()
748 __qman_requires_cleanup = 0; in qman_done_cleanup()
763 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); in fsl_qman_probe()
774 if (major == 1 && minor == 0) { in fsl_qman_probe()
775 dev_err(dev, "Rev1.0 on P4080 rev1 is not supported!\n"); in fsl_qman_probe()
781 else if (major == 2 && minor == 0) in fsl_qman_probe()
783 else if (major == 3 && minor == 0) in fsl_qman_probe()
794 if ((qman_ip_rev & 0xff00) >= QMAN_REV30) { in fsl_qman_probe()
815 ret = qbman_init_private_mem(dev, 0, &fqd_a, &fqd_sz); in fsl_qman_probe()
817 dev_err(dev, "qbman_init_private_mem() for FQD failed 0x%x\n", in fsl_qman_probe()
822 dev_dbg(dev, "Allocated FQD 0x%llx 0x%zx\n", fqd_a, fqd_sz); in fsl_qman_probe()
828 dev_err(dev, "qbman_init_private_mem() for PFDR failed 0x%x\n", in fsl_qman_probe()
833 dev_dbg(dev, "Allocated PFDR 0x%llx 0x%zx\n", pfdr_a, pfdr_sz); in fsl_qman_probe()
841 err_irq = platform_get_irq(pdev, 0); in fsl_qman_probe()
842 if (err_irq <= 0) { in fsl_qman_probe()
859 qm_ccsr_out(REG_ERR_ISR, 0xffffffff); in fsl_qman_probe()
861 qm_ccsr_out(REG_ERR_IER, 0xffffffff); in fsl_qman_probe()
863 qm_fqalloc = devm_gen_pool_create(dev, 0, -1, "qman-fqalloc"); in fsl_qman_probe()
870 qm_qpalloc = devm_gen_pool_create(dev, 0, -1, "qman-qpalloc"); in fsl_qman_probe()
877 qm_cgralloc = devm_gen_pool_create(dev, 0, -1, "qman-cgralloc"); in fsl_qman_probe()
898 return 0; in fsl_qman_probe()