34 #define dma_write32(VAL, REG) \  macro
241 		dma_write32(val | DMA_RST_SCSI, DMA_CSR);  in sbus_esp_reset_dma()
242 		dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);  in sbus_esp_reset_dma()
246 		dma_write32(DMA_RESET_FAS366, DMA_CSR);  in sbus_esp_reset_dma()
247 		dma_write32(DMA_RST_SCSI, DMA_CSR);  in sbus_esp_reset_dma()
276 		dma_write32(0, DMA_CSR);  in sbus_esp_reset_dma()
277 		dma_write32(esp->prev_hme_dmacsr, DMA_CSR);  in sbus_esp_reset_dma()
279 		dma_write32(0, DMA_ADDR);  in sbus_esp_reset_dma()
285 			dma_write32(val | DMA_3CLKS, DMA_CSR);  in sbus_esp_reset_dma()
297 		dma_write32(val, DMA_CSR);  in sbus_esp_reset_dma()
309 		dma_write32(val, DMA_CSR);  in sbus_esp_reset_dma()
318 	dma_write32(val | DMA_INT_ENAB, DMA_CSR);  in sbus_esp_reset_dma()
334 		dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);  in sbus_esp_dma_drain()
350 		dma_write32(DMA_RST_SCSI, DMA_CSR);  in sbus_esp_dma_invalidate()
357 		dma_write32(0, DMA_CSR);  in sbus_esp_dma_invalidate()
358 		dma_write32(esp->prev_hme_dmacsr, DMA_CSR);  in sbus_esp_dma_invalidate()
363 		dma_write32(0, DMA_ADDR);  in sbus_esp_dma_invalidate()
380 		dma_write32(val, DMA_CSR);  in sbus_esp_dma_invalidate()
382 		dma_write32(val, DMA_CSR);  in sbus_esp_dma_invalidate()
409 		dma_write32(dma_count, DMA_COUNT);  in sbus_esp_send_dma_cmd()
410 		dma_write32(addr, DMA_ADDR);  in sbus_esp_send_dma_cmd()
411 		dma_write32(csr, DMA_CSR);  in sbus_esp_send_dma_cmd()
419 		dma_write32(csr, DMA_CSR);  in sbus_esp_send_dma_cmd()
422 			dma_write32(end - addr, DMA_COUNT);  in sbus_esp_send_dma_cmd()
424 		dma_write32(addr, DMA_ADDR);  in sbus_esp_send_dma_cmd()
501 		dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);  in esp_sbus_probe_one()
565 	dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);  in esp_sbus_remove()