143 	MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);  in mvs_free_reg_set()
151 	return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);  in mvs_assign_reg_set()
160 		MVS_CHIP_DISP->phy_reset(mvi, no, hard);  in mvs_phys_reset()
182 		MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);  in mvs_phy_control()
186 		tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);  in mvs_phy_control()
189 		MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_HARD_RESET);  in mvs_phy_control()
193 		MVS_CHIP_DISP->phy_enable(mvi, phy_id);  in mvs_phy_control()
194 		MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_SOFT_RESET);  in mvs_phy_control()
198 		MVS_CHIP_DISP->phy_disable(mvi, phy_id);  in mvs_phy_control()
214 	MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);  in mvs_set_sas_addr()
215 	MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);  in mvs_set_sas_addr()
216 	MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);  in mvs_set_sas_addr()
217 	MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);  in mvs_set_sas_addr()
242 		sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();  in mvs_bytes_dmaed()
255 			MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);  in mvs_bytes_dmaed()
256 			MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x00);  in mvs_bytes_dmaed()
365 	i = MVS_CHIP_DISP->prd_size() * tei->n_elem;  in mvs_task_prep_smp()
396 	MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);  in mvs_task_prep_smp()
459 		flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);  in mvs_task_prep_ata()
509 	i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();  in mvs_task_prep_ata()
544 	MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);  in mvs_task_prep_ata()
547 		MVS_CHIP_DISP->dma_fix(mvi, sas_port->phy_mask,  in mvs_task_prep_ata()
621 	i = MVS_CHIP_DISP->prd_size() * tei->n_elem;  in mvs_task_prep_ssp()
684 	MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);  in mvs_task_prep_ssp()
854 			MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) &  in mvs_queue_command()
915 			MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,  in mvs_update_wideport()
917 			MVS_CHIP_DISP->write_port_cfg_data(mvi, no,  in mvs_update_wideport()
920 			MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,  in mvs_update_wideport()
922 			MVS_CHIP_DISP->write_port_cfg_data(mvi, no,  in mvs_update_wideport()
934 	tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);  in mvs_is_phy_ready()
963 	MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);  in mvs_get_d2h_reg()
964 	s[3] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));  in mvs_get_d2h_reg()
966 	MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);  in mvs_get_d2h_reg()
967 	s[2] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));  in mvs_get_d2h_reg()
969 	MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);  in mvs_get_d2h_reg()
970 	s[1] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));  in mvs_get_d2h_reg()
972 	MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);  in mvs_get_d2h_reg()
973 	s[0] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));  in mvs_get_d2h_reg()
1001 		phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);  in mvs_update_phyinfo()
1009 		oob_done = MVS_CHIP_DISP->oob_done(mvi, i);  in mvs_update_phyinfo()
1011 		MVS_CHIP_DISP->fix_phy_info(mvi, i, id);  in mvs_update_phyinfo()
1028 				tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);  in mvs_update_phyinfo()
1029 				MVS_CHIP_DISP->write_port_irq_mask(mvi, i,  in mvs_update_phyinfo()
1055 		if (MVS_CHIP_DISP->phy_work_around)  in mvs_update_phyinfo()
1056 			MVS_CHIP_DISP->phy_work_around(mvi, i);  in mvs_update_phyinfo()
1064 		MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);  in mvs_update_phyinfo()
1101 			MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);  in mvs_port_notify_formed()
1102 			MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x04);  in mvs_port_notify_formed()
1489 		MVS_CHIP_DISP->issue_stop(mvi, type, tfs);  in mvs_slot_err()
1491 	MVS_CHIP_DISP->command_active(mvi, slot_idx);  in mvs_slot_err()
1682 		MVS_CHIP_DISP->command_active(mvi, slot_idx);  in mvs_do_release_task()
1720 			tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);  in mvs_work_queue()
1729 				MVS_CHIP_DISP->detect_porttype(mvi, phy_no);  in mvs_work_queue()
1776 			MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_HARD_RESET);  in mvs_sig_time_out()
1786 	phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);  in mvs_int_port()
1787 	MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);  in mvs_int_port()
1789 		MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));  in mvs_int_port()
1810 			MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1);  in mvs_int_port()
1816 				if (MVS_CHIP_DISP->stp_reset)  in mvs_int_port()
1817 					MVS_CHIP_DISP->stp_reset(mvi,  in mvs_int_port()
1820 					MVS_CHIP_DISP->phy_reset(mvi,  in mvs_int_port()
1828 		tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);  in mvs_int_port()
1829 		MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,  in mvs_int_port()
1842 			MVS_CHIP_DISP->detect_porttype(mvi, phy_no);  in mvs_int_port()
1844 				tmp = MVS_CHIP_DISP->read_port_irq_mask(  in mvs_int_port()
1847 				MVS_CHIP_DISP->write_port_irq_mask(mvi,  in mvs_int_port()
1852 				MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_PHY_TUNE);  in mvs_int_port()
1894 		mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;  in mvs_int_rx()
1917 		MVS_CHIP_DISP->int_full(mvi);  in mvs_int_rx()
1927 	if (MVS_CHIP_DISP->gpio_write) {  in mvs_gpio_write()
1928 		return MVS_CHIP_DISP->gpio_write(mvs_prv, reg_type,  in mvs_gpio_write()