Lines Matching refs:mr32
249 tmp = mr32(MVS_PCS); in mvs_94xx_enable_xmt()
322 tmp = mr32(MVS_HST_CHIP_CONFIG); in mvs_94xx_sgpio_init()
372 tmp = mr32(MVS_PHY_CTL); in mvs_94xx_init()
380 cctl = mr32(MVS_CTL) & 0xFFFF; in mvs_94xx_init()
387 tmp = mr32(MVS_PHY_CTL); in mvs_94xx_init()
441 tmp = mr32(MVS_PA_VSR_PORT); in mvs_94xx_init()
502 cctl = mr32(MVS_CTL); in mvs_94xx_init()
509 tmp = mr32(MVS_PCS); in mvs_94xx_init()
597 tmp = mr32(MVS_GBL_CTL); in mvs_94xx_interrupt_enable()
612 tmp = mr32(MVS_GBL_CTL); in mvs_94xx_interrupt_disable()
628 stat = mr32(MVS_GBL_INT_STAT); in mvs_94xx_isr_status()
673 tmp = mr32(MVS_INT_STAT_SRS_0); in mvs_94xx_clear_srs_irq()
678 tmp = mr32(MVS_INT_STAT_SRS_1); in mvs_94xx_clear_srs_irq()
685 tmp = mr32(MVS_INT_STAT_SRS_1); in mvs_94xx_clear_srs_irq()
687 tmp = mr32(MVS_INT_STAT_SRS_0); in mvs_94xx_clear_srs_irq()
706 tmp = mr32(MVS_INT_STAT); in mvs_94xx_issue_stop()
708 tmp = mr32(MVS_PCS) | 0xFF00; in mvs_94xx_issue_stop()
719 err_0 = mr32(MVS_NON_NCQ_ERR_0); in mvs_94xx_non_spec_ncq_error()
720 err_1 = mr32(MVS_NON_NCQ_ERR_1); in mvs_94xx_non_spec_ncq_error()
915 tmp = mr32(MVS_STP_REG_SET_0); in mvs_94xx_clear_active_cmds()
918 tmp = mr32(MVS_STP_REG_SET_1); in mvs_94xx_clear_active_cmds()
927 return mr32(SPI_RD_DATA_REG_94XX); in mvs_94xx_spi_read_data()
977 dwTmp = mr32(SPI_CTRL_REG_94XX); in mvs_94xx_spi_waitdataready()