20 	reg = mr32(MVS_GBL_PORT_TYPE);  in mvs_64xx_detect_porttype()
33 	tmp = mr32(MVS_PCS);  in mvs_64xx_enable_xmt()
79 		reg = mr32(MVS_PHY_CTL);  in mvs_64xx_stp_reset()
129 		tmp = mr32(MVS_INT_STAT_SRS_0);  in mvs_64xx_clear_srs_irq()
135 		tmp = mr32(MVS_INT_STAT_SRS_0);  in mvs_64xx_clear_srs_irq()
152 	tmp = mr32(MVS_GBL_CTL);  in mvs_64xx_chip_reset()
171 	tmp = mr32(MVS_GBL_CTL);  in mvs_64xx_chip_reset()
184 		if (!(mr32(MVS_GBL_CTL) & HBA_RST))  in mvs_64xx_chip_reset()
187 	if (mr32(MVS_GBL_CTL) & HBA_RST) {  in mvs_64xx_chip_reset()
210 		tmp = mr32(MVS_PHY_CTL);  in mvs_64xx_phy_disable()
232 		tmp = mr32(MVS_PHY_CTL);  in mvs_64xx_phy_enable()
252 		tmp = mr32(MVS_PHY_CTL);  in mvs_64xx_init()
260 	cctl = mr32(MVS_CTL) & 0xFFFF;  in mvs_64xx_init()
283 		tmp = mr32(MVS_PHY_CTL);  in mvs_64xx_init()
362 	cctl = mr32(MVS_CTL);  in mvs_64xx_init()
370 	tmp = mr32(MVS_PCS);  in mvs_64xx_init()
425 	tmp = mr32(MVS_GBL_CTL);  in mvs_64xx_interrupt_enable()
434 	tmp = mr32(MVS_GBL_CTL);  in mvs_64xx_interrupt_disable()
444 		stat = mr32(MVS_GBL_INT_STAT);  in mvs_64xx_isr_status()
487 		tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs);  in mvs_64xx_issue_stop()
491 	tmp = mr32(MVS_PCS) | 0xFF00;  in mvs_64xx_issue_stop()
505 		tmp = mr32(MVS_PCS);  in mvs_64xx_free_reg_set()
508 		tmp = mr32(MVS_CTL);  in mvs_64xx_free_reg_set()
512 	tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << *tfs);  in mvs_64xx_free_reg_set()
529 	tmp = mr32(MVS_PCS);  in mvs_64xx_assign_reg_set()
533 			tmp = mr32(MVS_CTL);  in mvs_64xx_assign_reg_set()
542 			tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << i);  in mvs_64xx_assign_reg_set()
647 	tmp = mr32(MVS_PCS);  in mvs_64xx_clear_active_cmds()
650 	tmp = mr32(MVS_CTL);  in mvs_64xx_clear_active_cmds()