Lines Matching refs:SA5_REPLY_INTR_MASK_OFFSET
374 #define SA5_REPLY_INTR_MASK_OFFSET 0x34 macro
448 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()
449 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()
453 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()
454 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()
465 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5B_intr_mask()
466 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5B_intr_mask()
470 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5B_intr_mask()
471 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5B_intr_mask()
479 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()
480 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()
484 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()
485 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()