Lines Matching +full:0 +full:xc8
93 0x01, /* 0x00: Sub System Vendor ID 0 */
94 0x11, /* 0x01: Sub System Vendor ID 1 */
95 0x60, /* 0x02: Sub System ID 0 */
96 0x10, /* 0x03: Sub System ID 1 */
97 0x00, /* 0x04: SubClass */
98 0x01, /* 0x05: Vendor ID 0 */
99 0x11, /* 0x06: Vendor ID 1 */
100 0x60, /* 0x07: Device ID 0 */
101 0x10, /* 0x08: Device ID 1 */
102 0x00, /* 0x09: Reserved */
103 0x00, /* 0x0A: Reserved */
104 0x01, /* 0x0B: Revision of Data Structure */
106 0x01, /* 0x0C: Number Of SCSI Channel */
107 0x01, /* 0x0D: BIOS Configuration 1 */
108 0x00, /* 0x0E: BIOS Configuration 2 */
109 0x00, /* 0x0F: BIOS Configuration 3 */
110 /* --- SCSI Channel 0 Configuration --- */
111 0x07, /* 0x10: H/A ID */
112 0x83, /* 0x11: Channel Configuration */
113 0x20, /* 0x12: MAX TAG per target */
114 0x0A, /* 0x13: SCSI Reset Recovering time */
115 0x00, /* 0x14: Channel Configuration4 */
116 0x00, /* 0x15: Channel Configuration5 */
117 /* SCSI Channel 0 Target Configuration */
118 /* 0x16-0x25 */
119 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
120 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
122 0x07, /* 0x26: H/A ID */
123 0x83, /* 0x27: Channel Configuration */
124 0x20, /* 0x28: MAX TAG per target */
125 0x0A, /* 0x29: SCSI Reset Recovering time */
126 0x00, /* 0x2A: Channel Configuration4 */
127 0x00, /* 0x2B: Channel Configuration5 */
129 /* 0x2C-0x3B */
130 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
131 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
132 0x00, /* 0x3C: Reserved */
133 0x00, /* 0x3D: Reserved */
134 0x00, /* 0x3E: Reserved */
135 0x00 /* 0x3F: Checksum */
143 for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */ in wait_chip_ready()
148 return 0; in wait_chip_ready()
155 for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */ in wait_firmware_ready()
160 return 0; in wait_firmware_ready()
168 for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */ in wait_scsi_reset_done()
173 return 0; in wait_scsi_reset_done()
181 for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */ in wait_HDO_off()
186 return 0; in wait_HDO_off()
194 for (i = 0; i < 10; i++) { /* Wait 1 second for report timeout */ in wait_hdi_set()
199 return 0; in wait_hdi_set()
210 if (wait_HDO_off(host) == 0) /* Wait HDO off */ in orc_read_fwrev()
211 return 0; in orc_read_fwrev()
213 if (wait_hdi_set(host, &data) == 0) /* Wait HDI set */ in orc_read_fwrev()
214 return 0; in orc_read_fwrev()
218 if (wait_hdi_set(host, &data) == 0) /* Wait HDI set */ in orc_read_fwrev()
219 return 0; in orc_read_fwrev()
231 if (wait_HDO_off(host) == 0) /* Wait HDO off */ in orc_nv_write()
232 return 0; in orc_nv_write()
236 if (wait_HDO_off(host) == 0) /* Wait HDO off */ in orc_nv_write()
237 return 0; in orc_nv_write()
241 if (wait_HDO_off(host) == 0) /* Wait HDO off */ in orc_nv_write()
242 return 0; in orc_nv_write()
254 if (wait_HDO_off(host) == 0) /* Wait HDO off */ in orc_nv_read()
255 return 0; in orc_nv_read()
259 if (wait_HDO_off(host) == 0) /* Wait HDO off */ in orc_nv_read()
260 return 0; in orc_nv_read()
262 if (wait_hdi_set(host, &data) == 0) /* Wait HDI set */ in orc_nv_read()
263 return 0; in orc_nv_read()
294 u8 *np, chksum = 0; in se2_rd_all()
297 for (i = 0; i < 64; i++, np++) { /* <01> */ in se2_rd_all()
298 if (orc_nv_read(host, (u8) i, np) == 0) in se2_rd_all()
304 for (i = 0; i < 63; i++) in se2_rd_all()
322 u8 *np, *np1, chksum = 0; in se2_update_all()
326 for (i = 0; i < 63; i++) in se2_update_all()
332 for (i = 0; i < 64; i++, np++, np1++) { in se2_update_all()
377 outb(0x00, host->base + ORC_EBIOSADR2); in orc_load_firmware()
378 outw(0x0000, host->base + ORC_EBIOSADR0); in orc_load_firmware()
379 if (inb(host->base + ORC_EBIOSDATA) != 0x55) { in orc_load_firmware()
381 return 0; in orc_load_firmware()
383 outw(0x0001, host->base + ORC_EBIOSADR0); in orc_load_firmware()
384 if (inb(host->base + ORC_EBIOSDATA) != 0xAA) { in orc_load_firmware()
386 return 0; in orc_load_firmware()
391 data32 = cpu_to_le32(0); /* Initial FW address to 0 */ in orc_load_firmware()
392 outw(0x0010, host->base + ORC_EBIOSADR0); in orc_load_firmware()
394 outw(0x0011, host->base + ORC_EBIOSADR0); in orc_load_firmware()
396 outw(0x0012, host->base + ORC_EBIOSADR0); in orc_load_firmware()
405 for (i = 0, data32_ptr = (u8 *) & data32; /* Download the code */ in orc_load_firmware()
406 i < 0x1000; /* Firmware code size = 4K */ in orc_load_firmware()
418 outb(PRGMRST | DOWNLOAD, host->base + ORC_RISCCTL); /* Reset program count 0 */ in orc_load_firmware()
419 bios_addr -= 0x1000; /* Reset the BIOS address */ in orc_load_firmware()
420 for (i = 0, data32_ptr = (u8 *) & data32; /* Check the code */ in orc_load_firmware()
421 i < 0x1000; /* Firmware code size = 4K */ in orc_load_firmware()
427 outb(PRGMRST, host->base + ORC_RISCCTL); /* Reset program to 0 */ in orc_load_firmware()
429 return 0; in orc_load_firmware()
436 outb(PRGMRST, host->base + ORC_RISCCTL); /* Reset program to 0 */ in orc_load_firmware()
451 /* SCB base address 0 */ in setup_SCBs()
460 for (i = 0; i < ORC_MAXQUEUE; i++) { in setup_SCBs()
483 for (i = 0; i < MAX_CHANNELS; i++) { in init_alloc_map()
484 for (j = 0; j < 8; j++) { in init_alloc_map()
485 host->allocation_map[i][j] = 0xffffffff; in init_alloc_map()
506 outb(0xFF, host->base + ORC_GIMSK); /* Disable all interrupts */ in init_orchid()
510 if (revision == 0xFFFF) { in init_orchid()
512 if (wait_chip_ready(host) == 0) in init_orchid()
516 outb(0x00, host->base + ORC_HCTRL); /* clear HOSTSTOP */ in init_orchid()
517 if (wait_firmware_ready(host) == 0) in init_orchid()
525 if (wait_chip_ready(host) == 0) in init_orchid()
532 if (wait_firmware_ready(host) == 0) /* Wait for firmware ready */ in init_orchid()
547 for (i = 0; i < 16; ptr++, i++) { in init_orchid()
554 outb(0xFB, host->base + ORC_GIMSK); /* enable RP FIFO interrupt */ in init_orchid()
555 return 0; in init_orchid()
576 if (wait_scsi_reset_done(host) == 0) { in orc_reset_scsi_bus()
615 for (i = 0; i < ORC_MAXQUEUE; i++) { in orc_device_reset()
639 scb->hastat = 0; in orc_device_reset()
640 scb->tastat = 0; in orc_device_reset()
641 scb->status = 0x0; in orc_device_reset()
642 scb->link = 0xFF; in orc_device_reset()
643 scb->reserved0 = 0; in orc_device_reset()
644 scb->reserved1 = 0; in orc_device_reset()
645 scb->xferlen = cpu_to_le32(0); in orc_device_reset()
646 scb->sg_len = cpu_to_le32(0); in orc_device_reset()
673 for (i = 0; i < 8; i++) { in __orc_alloc_scb()
674 for (index = 0; index < 32; index++) { in __orc_alloc_scb()
675 if ((host->allocation_map[channel][i] >> index) & 0x01) { in __orc_alloc_scb()
744 if (wait_HDO_off(host) == 0) /* Wait HDO off */ in orchid_abort_scb()
745 return 0; in orchid_abort_scb()
749 if (wait_HDO_off(host) == 0) /* Wait HDO off */ in orchid_abort_scb()
750 return 0; in orchid_abort_scb()
752 if (wait_hdi_set(host, &data) == 0) /* Wait HDI set */ in orchid_abort_scb()
753 return 0; in orchid_abort_scb()
757 if (status == 1) /* 0 - Successfully */ in orchid_abort_scb()
758 return 0; /* 1 - Fail */ in orchid_abort_scb()
777 for (i = 0; i < ORC_MAXQUEUE; i++, scb++) { in inia100_abort_cmd()
780 if (scb->tag_msg == 0) { in inia100_abort_cmd()
817 if (inb(host->base + ORC_RQUEUECNT) == 0) in orc_interrupt()
826 scb->status = 0x0; in orc_interrupt()
859 scb->reserved0 = 0; in inia100_build_scb()
860 scb->reserved1 = 0; in inia100_build_scb()
861 scb->sg_len = cpu_to_le32(0); in inia100_build_scb()
864 sgent = (struct orc_sgent *) & escb->sglist[0]; in inia100_build_scb()
867 if (count_sg < 0) in inia100_build_scb()
880 scb->sg_len = cpu_to_le32(0); in inia100_build_scb()
881 sgent->base = cpu_to_le32(0); in inia100_build_scb()
882 sgent->length = cpu_to_le32(0); in inia100_build_scb()
885 scb->hastat = 0; in inia100_build_scb()
886 scb->tastat = 0; in inia100_build_scb()
887 scb->link = 0xFF; in inia100_build_scb()
894 scb->ident = (u8)(cmd->device->lun & 0xff) | DISC_ALLOW; in inia100_build_scb()
898 scb->tag_msg = 0; /* No tag support */ in inia100_build_scb()
901 return 0; in inia100_build_scb()
927 return 0; in inia100_queue_lck()
1002 case 0x0: in inia100_scb_handler()
1003 case 0xa: /* Linked command complete without error and linked normally */ in inia100_scb_handler()
1004 case 0xb: /* Linked command complete without error interrupt generated */ in inia100_scb_handler()
1005 scb->hastat = 0; in inia100_scb_handler()
1008 case 0x11: /* Selection time out-The initiator selection or target in inia100_scb_handler()
1013 case 0x14: /* Target bus phase sequence failure-An invalid bus phase or bus in inia100_scb_handler()
1020 case 0x1a: /* SCB Aborted. 07/21/98 */ in inia100_scb_handler()
1024 case 0x12: /* Data overrun/underrun-The target attempted to transfer more data in inia100_scb_handler()
1027 case 0x13: /* Unexpected bus free-The target dropped the SCSI BSY at an unexpected time. */ in inia100_scb_handler()
1028 case 0x16: /* Invalid CCB Operation Code-The first byte of the CCB was invalid. */ in inia100_scb_handler()
1037 memcpy((unsigned char *) &cmd->sense_buffer[0], in inia100_scb_handler()
1038 (unsigned char *) &escb->sglist[0], SENSE_SIZE); in inia100_scb_handler()
1099 port = pci_resource_start(pdev, 0); in inia100_probe_one()
1101 printk(KERN_WARNING "inia100: io port 0x%lx, is busy.\n", port); in inia100_probe_one()
1105 /* <02> read from base address + 0x50 offset to get the bios value. */ in inia100_probe_one()
1106 bios = inw(port + 0x50); in inia100_probe_one()
1143 shost->n_io_port = 0xff; in inia100_probe_one()
1155 if (error < 0) { in inia100_probe_one()
1168 return 0; in inia100_probe_one()
1210 {PCI_VENDOR_ID_INIT, 0x1060, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1211 {0,}