Lines Matching refs:reg_base
110 void __iomem *reg_base; member
161 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
163 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
166 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
168 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
171 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_reset()
180 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
182 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
187 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
190 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
192 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
196 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
199 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_reset()
202 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_reset()
208 val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_reset()
212 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
214 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
218 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
221 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
223 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
226 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_reset()
228 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_reset()
231 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
233 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
273 writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); in q6v5_wcss_start()
344 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
346 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
348 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_qcs404_power_on()
357 writel(0, wcss->reg_base + Q6SS_CGC_OVERRIDE); in q6v5_wcss_qcs404_power_on()
360 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_wcss_qcs404_power_on()
362 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_wcss_qcs404_power_on()
370 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_power_on()
372 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_power_on()
375 writel(0x01700000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
377 writel(0x03700000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
379 writel(0x03300000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
381 writel(0x033C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
388 writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) | in q6v5_wcss_qcs404_power_on()
389 (1 << idx)), wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_qcs404_power_on()
392 writel(0x031C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
393 writel(0x030C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
395 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_power_on()
397 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_power_on()
400 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
402 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
412 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
414 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
417 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_wcss_qcs404_power_on()
419 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_wcss_qcs404_power_on()
421 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
423 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
445 writel(0x80800000, wcss->reg_base + Q6SS_STRAP_ACC); in q6v5_wcss_qcs404_reset()
448 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_reset()
450 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_reset()
476 writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); in q6v5_qcs404_wcss_start()
538 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_qcs404_wcss_shutdown()
540 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_qcs404_wcss_shutdown()
543 writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) & in q6v5_qcs404_wcss_shutdown()
545 wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_qcs404_wcss_shutdown()
548 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_qcs404_wcss_shutdown()
550 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_qcs404_wcss_shutdown()
558 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_qcs404_wcss_shutdown()
560 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_qcs404_wcss_shutdown()
562 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_qcs404_wcss_shutdown()
564 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_qcs404_wcss_shutdown()
569 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_qcs404_wcss_shutdown()
571 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_qcs404_wcss_shutdown()
650 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_q6_powerdown()
652 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_q6_powerdown()
655 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
657 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
661 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
665 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
669 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
673 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_q6_powerdown()
675 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_q6_powerdown()
680 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
682 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
686 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
690 ret = readl_poll_timeout(wcss->reg_base + Q6SS_BHS_STATUS, in q6v5_q6_powerdown()
834 wcss->reg_base = devm_ioremap(&pdev->dev, res->start, in q6v5_wcss_init_mmio()
836 if (!wcss->reg_base) in q6v5_wcss_init_mmio()