Lines Matching +full:msm8953 +full:- +full:mss +full:- +full:pil
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Qualcomm self-authenticating modem subsystem remoteproc driver
7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
13 #include <linux/dma-mapping.h>
273 if (rc != -EPROBE_DEFER)
297 dev_err(qproc->dev,
308 dev_err(qproc->dev,
316 dev_err(qproc->dev, "Regulator enable failed\n");
323 for (; i >= 0; i--) {
368 for (i--; i >= 0; i--)
402 for (i--; i >= 0; i--) {
428 if (!qproc->need_mem_protection)
455 if (request_firmware_direct(&dp_fw, "msadp", qproc->dev))
458 if (SZ_1M + dp_fw->size <= qproc->mba_size) {
459 memcpy(mba_region + SZ_1M, dp_fw->data, dp_fw->size);
460 qproc->dp_size = dp_fw->size;
468 struct q6v5 *qproc = rproc->priv;
472 if (fw->size > qproc->mba_size || fw->size > SZ_1M) {
473 dev_err(qproc->dev, "MBA firmware load failed\n");
474 return -EINVAL;
477 mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC);
479 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
480 &qproc->mba_phys, qproc->mba_size);
481 return -EBUSY;
484 memcpy(mba_region, fw->data, fw->size);
495 if (qproc->has_alt_reset) {
496 reset_control_assert(qproc->pdc_reset);
497 ret = reset_control_reset(qproc->mss_restart);
498 reset_control_deassert(qproc->pdc_reset);
499 } else if (qproc->has_spare_reg) {
505 * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE
506 * is withdrawn post MSS assert followed by a MSS deassert,
509 reset_control_assert(qproc->pdc_reset);
510 regmap_update_bits(qproc->conn_map, qproc->conn_box,
512 reset_control_assert(qproc->mss_restart);
513 reset_control_deassert(qproc->pdc_reset);
514 regmap_update_bits(qproc->conn_map, qproc->conn_box,
516 ret = reset_control_deassert(qproc->mss_restart);
517 } else if (qproc->has_ext_cntl_regs) {
518 regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
519 reset_control_assert(qproc->pdc_reset);
520 reset_control_assert(qproc->mss_restart);
521 reset_control_deassert(qproc->pdc_reset);
522 ret = reset_control_deassert(qproc->mss_restart);
524 ret = reset_control_assert(qproc->mss_restart);
534 if (qproc->has_alt_reset) {
535 reset_control_assert(qproc->pdc_reset);
536 writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
537 ret = reset_control_reset(qproc->mss_restart);
538 writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
539 reset_control_deassert(qproc->pdc_reset);
540 } else if (qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
541 ret = reset_control_reset(qproc->mss_restart);
543 ret = reset_control_deassert(qproc->mss_restart);
556 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
561 return -ETIMEDOUT;
577 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
587 return -ETIMEDOUT;
597 struct rproc *rproc = qproc->rproc;
601 if (!qproc->has_mba_logs)
604 if (q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, qproc->mba_phys,
605 qproc->mba_size))
608 mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC);
615 dev_coredumpv(&rproc->dev, data, MBA_LOG_SIZE, GFP_KERNEL);
626 if (qproc->version == MSS_SDM845) {
627 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
629 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
631 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
635 dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
636 return -ETIMEDOUT;
639 /* De-assert QDSP6 stop core */
640 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
642 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
644 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
647 dev_err(qproc->dev, "Boot FSM failed to complete.\n");
654 } else if (qproc->version == MSS_SC7180 || qproc->version == MSS_SC7280) {
655 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
657 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
659 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
663 dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
664 return -ETIMEDOUT;
668 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
670 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
672 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
676 dev_err(qproc->dev, "QDSP6SS XO clock timed out\n");
677 return -ETIMEDOUT;
680 /* Configure Q6 core CBCR to auto-enable after reset sequence */
681 val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
683 writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
685 /* De-assert the Q6 stop core signal */
686 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
691 /* Trigger the boot FSM to start the Q6 out-of-reset sequence */
692 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
695 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
698 dev_err(qproc->dev, "Boot FSM failed to complete.\n");
704 } else if (qproc->version == MSS_MSM8909 ||
705 qproc->version == MSS_MSM8953 ||
706 qproc->version == MSS_MSM8996 ||
707 qproc->version == MSS_MSM8998 ||
708 qproc->version == MSS_SDM660) {
710 if (qproc->version != MSS_MSM8909 &&
711 qproc->version != MSS_MSM8953)
714 qproc->reg_base + QDSP6SS_STRAP_ACC);
717 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
719 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
722 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
724 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
727 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
731 dev_err(qproc->dev,
736 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
738 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
739 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
742 if (qproc->version == MSS_SDM660) {
743 ret = readl_relaxed_poll_timeout(qproc->reg_base + QDSP6V62SS_BHS_STATUS,
746 if (ret == -ETIMEDOUT) {
747 dev_err(qproc->dev, "BHS_EN_REST_ACK not set!\n");
748 return -ETIMEDOUT;
754 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
756 if (qproc->version != MSS_MSM8909) {
760 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
762 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
766 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
769 if (qproc->version == MSS_MSM8953 ||
770 qproc->version == MSS_MSM8996) {
778 val = readl(qproc->reg_base + mem_pwr_ctl);
779 for (; i >= 0; i--) {
781 writel(val, qproc->reg_base + mem_pwr_ctl);
787 val |= readl(qproc->reg_base + mem_pwr_ctl);
792 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
795 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
800 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
805 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
807 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
810 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
812 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
815 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
817 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
818 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
824 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
827 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
829 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
831 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
833 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
837 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
840 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
842 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
845 val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
847 writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
850 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
852 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
857 if (ret == -ETIMEDOUT) {
858 dev_err(qproc->dev, "PBL boot timed out\n");
860 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
861 ret = -EINVAL;
874 if (!qproc->has_qaccept_regs)
877 if (qproc->has_ext_cntl_regs) {
878 regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
879 regmap_write(qproc->conn_map, qproc->force_clk_on, 1);
881 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
884 dev_err(qproc->dev, "failed to enable axim1 clock\n");
885 return -ETIMEDOUT;
895 dev_err(qproc->dev, "qchannel enable failed\n");
896 return -ETIMEDOUT;
909 if (!qproc->has_qaccept_regs)
913 nretry--;
919 /* Request Q-channel transaction takedown */
923 * If the request is denied, reset the Q-channel takedown request,
929 retry--;
949 dev_err(qproc->dev, "qchannel takedown failed\n");
973 dev_err(qproc->dev, "port failed halt\n");
991 metadata = qcom_mdt_read_metadata(fw, &size, fw_name, qproc->dev);
995 if (qproc->mdata_phys) {
996 if (size > qproc->mdata_size) {
997 ret = -EINVAL;
998 dev_err(qproc->dev, "metadata size outside memory range\n");
1002 phys = qproc->mdata_phys;
1003 ptr = memremap(qproc->mdata_phys, size, MEMREMAP_WC);
1005 ret = -EBUSY;
1006 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
1007 &qproc->mdata_phys, size);
1011 ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
1013 ret = -ENOMEM;
1014 dev_err(qproc->dev, "failed to allocate mdt buffer\n");
1021 if (qproc->mdata_phys)
1029 dev_err(qproc->dev,
1031 ret = -EAGAIN;
1035 writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
1036 writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
1039 if (ret == -ETIMEDOUT)
1040 dev_err(qproc->dev, "MPSS header authentication timed out\n");
1042 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
1048 dev_warn(qproc->dev,
1052 if (!qproc->mdata_phys)
1053 dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs);
1062 if (phdr->p_type != PT_LOAD)
1065 if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
1068 if (!phdr->p_memsz)
1080 ret = qcom_q6v5_prepare(&qproc->q6v5);
1084 ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1086 dev_err(qproc->dev, "failed to enable proxy power domains\n");
1090 ret = q6v5_regulator_enable(qproc, qproc->fallback_proxy_regs,
1091 qproc->fallback_proxy_reg_count);
1093 dev_err(qproc->dev, "failed to enable fallback proxy supplies\n");
1097 ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
1098 qproc->proxy_reg_count);
1100 dev_err(qproc->dev, "failed to enable proxy supplies\n");
1104 ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
1105 qproc->proxy_clk_count);
1107 dev_err(qproc->dev, "failed to enable proxy clocks\n");
1111 ret = q6v5_regulator_enable(qproc, qproc->active_regs,
1112 qproc->active_reg_count);
1114 dev_err(qproc->dev, "failed to enable supplies\n");
1118 ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
1119 qproc->reset_clk_count);
1121 dev_err(qproc->dev, "failed to enable reset clocks\n");
1127 dev_err(qproc->dev, "failed to deassert mss restart\n");
1131 ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
1132 qproc->active_clk_count);
1134 dev_err(qproc->dev, "failed to enable clocks\n");
1138 ret = q6v5proc_enable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1140 dev_err(qproc->dev, "failed to enable axi bridge\n");
1148 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
1149 qproc->mpss_phys, qproc->mpss_size);
1151 dev_err(qproc->dev, "assigning Q6 access to mpss memory failed: %d\n", ret);
1156 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, true,
1157 qproc->mba_phys, qproc->mba_size);
1159 dev_err(qproc->dev,
1164 if (qproc->has_mba_logs)
1165 qcom_pil_info_store("mba", qproc->mba_phys, MBA_LOG_SIZE);
1167 writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
1168 if (qproc->dp_size) {
1169 writel(qproc->mba_phys + SZ_1M, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1170 writel(qproc->dp_size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1178 if (ret == -ETIMEDOUT) {
1179 dev_err(qproc->dev, "MBA boot timed out\n");
1183 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
1184 ret = -EINVAL;
1188 qproc->dump_mba_loaded = true;
1192 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1193 if (qproc->has_vq6)
1194 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
1195 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1196 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1197 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
1198 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
1199 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1202 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1203 false, qproc->mba_phys,
1204 qproc->mba_size);
1206 dev_err(qproc->dev,
1213 q6v5_clk_disable(qproc->dev, qproc->active_clks,
1214 qproc->active_clk_count);
1218 q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1219 qproc->reset_clk_count);
1221 q6v5_regulator_disable(qproc, qproc->active_regs,
1222 qproc->active_reg_count);
1224 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1225 qproc->proxy_clk_count);
1227 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1228 qproc->proxy_reg_count);
1230 q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1231 qproc->fallback_proxy_reg_count);
1233 q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1235 qcom_q6v5_unprepare(&qproc->q6v5);
1245 qproc->dump_mba_loaded = false;
1246 qproc->dp_size = 0;
1248 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1249 if (qproc->has_vq6)
1250 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
1251 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1252 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1253 if (qproc->version == MSS_MSM8996) {
1255 * To avoid high MX current during LPASS/MSS restart.
1257 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1260 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1263 if (qproc->has_ext_cntl_regs) {
1264 regmap_write(qproc->conn_map, qproc->rscc_disable, 1);
1266 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
1269 dev_err(qproc->dev, "failed to enable axim1 clock\n");
1271 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->crypto_clk_off, val,
1274 dev_err(qproc->dev, "failed to enable crypto clock\n");
1277 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
1278 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
1279 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1283 q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1284 qproc->reset_clk_count);
1285 q6v5_clk_disable(qproc->dev, qproc->active_clks,
1286 qproc->active_clk_count);
1287 q6v5_regulator_disable(qproc, qproc->active_regs,
1288 qproc->active_reg_count);
1293 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false,
1294 qproc->mba_phys,
1295 qproc->mba_size);
1298 ret = qcom_q6v5_unprepare(&qproc->q6v5);
1300 q6v5_pds_disable(qproc, qproc->proxy_pds,
1301 qproc->proxy_pd_count);
1302 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1303 qproc->proxy_clk_count);
1304 q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1305 qproc->fallback_proxy_reg_count);
1306 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1307 qproc->proxy_reg_count);
1313 struct q6v5 *qproc = rproc->priv;
1317 ret = request_firmware(&fw, rproc->firmware, qproc->dev);
1349 fw_name_len = strlen(qproc->hexagon_mdt_image);
1351 return -EINVAL;
1353 fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL);
1355 return -ENOMEM;
1357 ret = request_firmware(&fw, fw_name, qproc->dev);
1359 dev_err(qproc->dev, "unable to load %s\n", fw_name);
1364 writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1366 ret = q6v5_mpss_init_image(qproc, fw, qproc->hexagon_mdt_image);
1370 ehdr = (struct elf32_hdr *)fw->data;
1373 for (i = 0; i < ehdr->e_phnum; i++) {
1379 if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
1382 if (phdr->p_paddr < min_addr)
1383 min_addr = phdr->p_paddr;
1385 if (phdr->p_paddr + phdr->p_memsz > max_addr)
1386 max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
1389 if (qproc->version == MSS_MSM8953) {
1390 ret = qcom_scm_pas_mem_setup(MPSS_PAS_ID, qproc->mpss_phys, qproc->mpss_size);
1392 dev_err(qproc->dev,
1402 q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, false,
1403 qproc->mpss_phys, qproc->mpss_size);
1405 /* Share ownership between Linux and MSS, during segment loading */
1406 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, true,
1407 qproc->mpss_phys, qproc->mpss_size);
1409 dev_err(qproc->dev,
1411 ret = -EAGAIN;
1415 mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
1416 qproc->mpss_reloc = mpss_reloc;
1418 for (i = 0; i < ehdr->e_phnum; i++) {
1424 offset = phdr->p_paddr - mpss_reloc;
1425 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
1426 dev_err(qproc->dev, "segment outside memory range\n");
1427 ret = -EINVAL;
1431 if (phdr->p_filesz > phdr->p_memsz) {
1432 dev_err(qproc->dev,
1435 ret = -EINVAL;
1439 ptr = memremap(qproc->mpss_phys + offset, phdr->p_memsz, MEMREMAP_WC);
1441 dev_err(qproc->dev,
1442 "unable to map memory region: %pa+%zx-%x\n",
1443 &qproc->mpss_phys, offset, phdr->p_memsz);
1447 if (phdr->p_filesz && phdr->p_offset < fw->size) {
1448 /* Firmware is large enough to be non-split */
1449 if (phdr->p_offset + phdr->p_filesz > fw->size) {
1450 dev_err(qproc->dev,
1453 ret = -EINVAL;
1458 memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz);
1459 } else if (phdr->p_filesz) {
1461 sprintf(fw_name + fw_name_len - 3, "b%02d", i);
1462 ret = request_firmware_into_buf(&seg_fw, fw_name, qproc->dev,
1463 ptr, phdr->p_filesz);
1465 dev_err(qproc->dev, "failed to load %s\n", fw_name);
1470 if (seg_fw->size != phdr->p_filesz) {
1471 dev_err(qproc->dev,
1474 ret = -EINVAL;
1483 if (phdr->p_memsz > phdr->p_filesz) {
1484 memset(ptr + phdr->p_filesz, 0,
1485 phdr->p_memsz - phdr->p_filesz);
1488 size += phdr->p_memsz;
1490 code_length = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1492 boot_addr = relocate ? qproc->mpss_phys : min_addr;
1493 writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1494 writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
1496 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1498 ret = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
1500 dev_err(qproc->dev, "MPSS authentication failed: %d\n",
1507 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
1508 qproc->mpss_phys, qproc->mpss_size);
1510 dev_err(qproc->dev,
1512 ret = -EAGAIN;
1517 if (ret == -ETIMEDOUT)
1518 dev_err(qproc->dev, "MPSS authentication timed out\n");
1520 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
1522 qcom_pil_info_store("modem", qproc->mpss_phys, qproc->mpss_size);
1537 struct q6v5 *qproc = rproc->priv;
1538 int offset = segment->da - qproc->mpss_reloc;
1542 if (!qproc->dump_mba_loaded) {
1546 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1548 qproc->mpss_phys,
1549 qproc->mpss_size);
1554 ptr = memremap(qproc->mpss_phys + offset + cp_offset, size, MEMREMAP_WC);
1563 qproc->current_dump_size += size;
1566 if (qproc->current_dump_size == qproc->total_dump_size) {
1567 if (qproc->dump_mba_loaded) {
1569 q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1571 qproc->mpss_phys,
1572 qproc->mpss_size);
1580 struct q6v5 *qproc = rproc->priv;
1588 dev_info(qproc->dev, "MBA booted with%s debug policy, loading mpss\n",
1589 qproc->dp_size ? "" : "out");
1595 ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
1596 if (ret == -ETIMEDOUT) {
1597 dev_err(qproc->dev, "start timed out\n");
1601 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1602 false, qproc->mba_phys,
1603 qproc->mba_size);
1605 dev_err(qproc->dev,
1609 qproc->current_dump_size = 0;
1622 struct q6v5 *qproc = rproc->priv;
1625 ret = qcom_q6v5_request_stop(&qproc->q6v5, qproc->sysmon);
1626 if (ret == -ETIMEDOUT)
1627 dev_err(qproc->dev, "timed out on wait\n");
1641 struct q6v5 *qproc = rproc->priv;
1645 ret = request_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev);
1647 dev_err(qproc->dev, "unable to load %s\n",
1648 qproc->hexagon_mdt_image);
1654 ehdr = (struct elf32_hdr *)fw->data;
1656 qproc->total_dump_size = 0;
1658 for (i = 0; i < ehdr->e_phnum; i++) {
1664 ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
1665 phdr->p_memsz,
1671 qproc->total_dump_size += phdr->p_memsz;
1680 struct q6v5 *qproc = rproc->priv;
1682 return qcom_q6v5_panic(&qproc->q6v5);
1697 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1698 qproc->proxy_clk_count);
1699 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1700 qproc->proxy_reg_count);
1701 q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1702 qproc->fallback_proxy_reg_count);
1703 q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1712 qproc->reg_base = devm_platform_ioremap_resource_byname(pdev, "qdsp6");
1713 if (IS_ERR(qproc->reg_base))
1714 return PTR_ERR(qproc->reg_base);
1716 qproc->rmb_base = devm_platform_ioremap_resource_byname(pdev, "rmb");
1717 if (IS_ERR(qproc->rmb_base))
1718 return PTR_ERR(qproc->rmb_base);
1720 if (qproc->has_vq6)
1723 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1724 "qcom,halt-regs", halt_cell_cnt, 0, &args);
1726 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
1727 return -EINVAL;
1730 qproc->halt_map = syscon_node_to_regmap(args.np);
1732 if (IS_ERR(qproc->halt_map))
1733 return PTR_ERR(qproc->halt_map);
1735 qproc->halt_q6 = args.args[0];
1736 qproc->halt_modem = args.args[1];
1737 qproc->halt_nc = args.args[2];
1739 if (qproc->has_vq6)
1740 qproc->halt_vq6 = args.args[3];
1742 if (qproc->has_qaccept_regs) {
1743 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1744 "qcom,qaccept-regs",
1747 dev_err(&pdev->dev, "failed to parse qaccept-regs\n");
1748 return -EINVAL;
1751 qproc->qaccept_mdm = args.args[0];
1752 qproc->qaccept_cx = args.args[1];
1753 qproc->qaccept_axi = args.args[2];
1756 if (qproc->has_ext_cntl_regs) {
1757 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1758 "qcom,ext-regs",
1761 dev_err(&pdev->dev, "failed to parse ext-regs index 0\n");
1762 return -EINVAL;
1765 qproc->conn_map = syscon_node_to_regmap(args.np);
1767 if (IS_ERR(qproc->conn_map))
1768 return PTR_ERR(qproc->conn_map);
1770 qproc->force_clk_on = args.args[0];
1771 qproc->rscc_disable = args.args[1];
1773 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1774 "qcom,ext-regs",
1777 dev_err(&pdev->dev, "failed to parse ext-regs index 1\n");
1778 return -EINVAL;
1781 qproc->axim1_clk_off = args.args[0];
1782 qproc->crypto_clk_off = args.args[1];
1785 if (qproc->has_spare_reg) {
1786 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1787 "qcom,spare-regs",
1790 dev_err(&pdev->dev, "failed to parse spare-regs\n");
1791 return -EINVAL;
1794 qproc->conn_map = syscon_node_to_regmap(args.np);
1796 if (IS_ERR(qproc->conn_map))
1797 return PTR_ERR(qproc->conn_map);
1799 qproc->conn_box = args.args[0];
1818 if (rc != -EPROBE_DEFER)
1842 if (num_pds == 1 && dev->pm_domain) {
1851 ret = PTR_ERR(devs[i]) ? : -ENODATA;
1859 for (i--; i >= 0; i--)
1868 struct device *dev = qproc->dev;
1872 if (pd_count == 1 && dev->pm_domain) {
1883 qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
1885 if (IS_ERR(qproc->mss_restart)) {
1886 dev_err(qproc->dev, "failed to acquire mss restart\n");
1887 return PTR_ERR(qproc->mss_restart);
1890 if (qproc->has_alt_reset || qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
1891 qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
1893 if (IS_ERR(qproc->pdc_reset)) {
1894 dev_err(qproc->dev, "failed to acquire pdc reset\n");
1895 return PTR_ERR(qproc->pdc_reset);
1909 * In the absence of mba/mpss sub-child, extract the mba and mpss
1910 * reserved memory regions from device's memory-region property.
1912 child = of_get_child_by_name(qproc->dev->of_node, "mba");
1914 node = of_parse_phandle(qproc->dev->of_node,
1915 "memory-region", 0);
1917 node = of_parse_phandle(child, "memory-region", 0);
1922 dev_err(qproc->dev, "no mba memory-region specified\n");
1923 return -EINVAL;
1929 dev_err(qproc->dev, "unable to resolve mba region\n");
1930 return -EINVAL;
1933 qproc->mba_phys = rmem->base;
1934 qproc->mba_size = rmem->size;
1937 node = of_parse_phandle(qproc->dev->of_node,
1938 "memory-region", 1);
1940 child = of_get_child_by_name(qproc->dev->of_node, "mpss");
1941 node = of_parse_phandle(child, "memory-region", 0);
1946 dev_err(qproc->dev, "no mpss memory-region specified\n");
1947 return -EINVAL;
1953 dev_err(qproc->dev, "unable to resolve mpss region\n");
1954 return -EINVAL;
1957 qproc->mpss_phys = qproc->mpss_reloc = rmem->base;
1958 qproc->mpss_size = rmem->size;
1961 node = of_parse_phandle(qproc->dev->of_node, "memory-region", 2);
1963 child = of_get_child_by_name(qproc->dev->of_node, "metadata");
1964 node = of_parse_phandle(child, "memory-region", 0);
1973 dev_err(qproc->dev, "unable to resolve metadata region\n");
1974 return -EINVAL;
1977 qproc->mdata_phys = rmem->base;
1978 qproc->mdata_size = rmem->size;
1992 desc = of_device_get_match_data(&pdev->dev);
1994 return -EINVAL;
1996 if (desc->need_mem_protection && !qcom_scm_is_available())
1997 return -EPROBE_DEFER;
1999 mba_image = desc->hexagon_mba_image;
2000 ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
2002 if (ret < 0 && ret != -EINVAL) {
2003 dev_err(&pdev->dev, "unable to read mba firmware-name\n");
2007 rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
2010 dev_err(&pdev->dev, "failed to allocate rproc\n");
2011 return -ENOMEM;
2014 rproc->auto_boot = false;
2017 qproc = rproc->priv;
2018 qproc->dev = &pdev->dev;
2019 qproc->rproc = rproc;
2020 qproc->hexagon_mdt_image = "modem.mdt";
2021 ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
2022 1, &qproc->hexagon_mdt_image);
2023 if (ret < 0 && ret != -EINVAL) {
2024 dev_err(&pdev->dev, "unable to read mpss firmware-name\n");
2030 qproc->has_qaccept_regs = desc->has_qaccept_regs;
2031 qproc->has_ext_cntl_regs = desc->has_ext_cntl_regs;
2032 qproc->has_vq6 = desc->has_vq6;
2033 qproc->has_spare_reg = desc->has_spare_reg;
2042 ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
2043 desc->proxy_clk_names);
2045 dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
2048 qproc->proxy_clk_count = ret;
2050 ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
2051 desc->reset_clk_names);
2053 dev_err(&pdev->dev, "Failed to get reset clocks.\n");
2056 qproc->reset_clk_count = ret;
2058 ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
2059 desc->active_clk_names);
2061 dev_err(&pdev->dev, "Failed to get active clocks.\n");
2064 qproc->active_clk_count = ret;
2066 ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
2067 desc->proxy_supply);
2069 dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
2072 qproc->proxy_reg_count = ret;
2074 ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs,
2075 desc->active_supply);
2077 dev_err(&pdev->dev, "Failed to get active regulators.\n");
2080 qproc->active_reg_count = ret;
2082 ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
2083 desc->proxy_pd_names);
2085 if (ret == -ENODATA && desc->fallback_proxy_supply) {
2086 ret = q6v5_regulator_init(&pdev->dev,
2087 qproc->fallback_proxy_regs,
2088 desc->fallback_proxy_supply);
2090 dev_err(&pdev->dev, "Failed to get fallback proxy regulators.\n");
2093 qproc->fallback_proxy_reg_count = ret;
2095 dev_err(&pdev->dev, "Failed to init power domains\n");
2098 qproc->proxy_pd_count = ret;
2101 qproc->has_alt_reset = desc->has_alt_reset;
2106 qproc->version = desc->version;
2107 qproc->need_mem_protection = desc->need_mem_protection;
2108 qproc->has_mba_logs = desc->has_mba_logs;
2110 ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM, "modem",
2115 qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
2116 qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
2117 qcom_add_glink_subdev(rproc, &qproc->glink_subdev, "mpss");
2118 qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
2119 qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
2120 qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
2121 if (IS_ERR(qproc->sysmon)) {
2122 ret = PTR_ERR(qproc->sysmon);
2130 node = of_get_compatible_child(pdev->dev.of_node, "qcom,bam-dmux");
2131 qproc->bam_dmux = of_platform_device_create(node, NULL, &pdev->dev);
2137 qcom_remove_sysmon_subdev(qproc->sysmon);
2139 qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
2140 qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
2141 qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
2143 q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
2153 struct rproc *rproc = qproc->rproc;
2155 if (qproc->bam_dmux)
2156 of_platform_device_destroy(&qproc->bam_dmux->dev, NULL);
2159 qcom_q6v5_deinit(&qproc->q6v5);
2160 qcom_remove_sysmon_subdev(qproc->sysmon);
2161 qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
2162 qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
2163 qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
2165 q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
2190 "mss",
2218 "mss",
2284 "mss",
2468 "mss",
2503 .supply = "mss",
2534 { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
2535 { .compatible = "qcom,msm8909-mss-pil", .data = &msm8909_mss},
2536 { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
2537 { .compatible = "qcom,msm8953-mss-pil", .data = &msm8953_mss},
2538 { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
2539 { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
2540 { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
2541 { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
2542 { .compatible = "qcom,sc7280-mss-pil", .data = &sc7280_mss},
2543 { .compatible = "qcom,sdm660-mss-pil", .data = &sdm660_mss},
2544 { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
2553 .name = "qcom-q6v5-mss",
2559 MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver");