57 	struct rz_mtu3_channel *mtu;  member
102 	*pv_val = rz_mtu3_16bit_ch_read(priv->mtu, reg_pv_offset);  in rz_mtu3_pwm_read_tgr_registers()
103 	*dc_val = rz_mtu3_16bit_ch_read(priv->mtu, reg_dc_offset);  in rz_mtu3_pwm_read_tgr_registers()
110 	rz_mtu3_16bit_ch_write(priv->mtu, reg_pv_offset, pv_val);  in rz_mtu3_pwm_write_tgr_registers()
111 	rz_mtu3_16bit_ch_write(priv->mtu, reg_dc_offset, dc_val);  in rz_mtu3_pwm_write_tgr_registers()
155 	is_channel_en = rz_mtu3_is_enabled(priv->mtu);  in rz_mtu3_pwm_is_ch_enabled()
160 		val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TIORH);  in rz_mtu3_pwm_is_ch_enabled()
162 		val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TIORL);  in rz_mtu3_pwm_is_ch_enabled()
184 		is_mtu3_channel_available = rz_mtu3_request_channel(priv->mtu);  in rz_mtu3_pwm_request()
209 		rz_mtu3_release_channel(priv->mtu);  in rz_mtu3_pwm_free()
230 	rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TMDR1, RZ_MTU3_TMDR1_MD_PWMMODE1);  in rz_mtu3_pwm_enable()
232 		rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORH, val);  in rz_mtu3_pwm_enable()
234 		rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORL, val);  in rz_mtu3_pwm_enable()
238 		rz_mtu3_enable(priv->mtu);  in rz_mtu3_pwm_enable()
257 		rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORH, RZ_MTU3_TIOR_OC_RETAIN);  in rz_mtu3_pwm_disable()
259 		rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORL, RZ_MTU3_TIOR_OC_RETAIN);  in rz_mtu3_pwm_disable()
264 		rz_mtu3_disable(priv->mtu);  in rz_mtu3_pwm_disable()
296 		val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TCR);  in rz_mtu3_pwm_get_state()
374 		rz_mtu3_disable(priv->mtu);  in rz_mtu3_pwm_config()
377 		rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TCR,  in rz_mtu3_pwm_config()
382 		rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TCR,  in rz_mtu3_pwm_config()
397 			rz_mtu3_enable(priv->mtu);  in rz_mtu3_pwm_config()
491 		rz_mtu3_pwm->channel_data[j].mtu = &parent_ddata->channels[i];  in rz_mtu3_pwm_probe()
492 		rz_mtu3_pwm->channel_data[j].mtu->dev = dev;  in rz_mtu3_pwm_probe()