Lines Matching +full:mtu1 +full:- +full:mtu2
1 // SPDX-License-Identifier: GPL-2.0
8 …* https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?lang…
11 * - When PWM is disabled, the output is driven to Hi-Z.
12 * - While the hardware supports both polarities, the driver (for now)
14 * - HW uses one counter and two match components to configure duty_cycle
16 * - Multi-Function Timer Pulse Unit (a.k.a MTU) has 7 HW channels for PWM
18 * - MTU{1, 2} channels have a single IO, whereas all other HW channels have
20 * - Each IO is modelled as an independent PWM channel.
21 * - rz_mtu3_channel_io_map table is used to map the PWM channel to the
29 #include <linux/mfd/rz-mtu3.h>
40 * struct rz_mtu3_channel_io_map - MTU3 pwm channel map
51 * struct rz_mtu3_pwm_channel - MTU3 pwm channel data
62 * struct rz_mtu3_pwm_chip - MTU3 pwm private data
86 * The MTU channels are {0..4, 6, 7} and the number of IO on MTU1
87 * and MTU2 channel is 1 compared to 2 on others.
102 *pv_val = rz_mtu3_16bit_ch_read(priv->mtu, reg_pv_offset); in rz_mtu3_pwm_read_tgr_registers()
103 *dc_val = rz_mtu3_16bit_ch_read(priv->mtu, reg_dc_offset); in rz_mtu3_pwm_read_tgr_registers()
110 rz_mtu3_16bit_ch_write(priv->mtu, reg_pv_offset, pv_val); in rz_mtu3_pwm_write_tgr_registers()
111 rz_mtu3_16bit_ch_write(priv->mtu, reg_dc_offset, dc_val); in rz_mtu3_pwm_write_tgr_registers()
136 struct rz_mtu3_pwm_channel *priv = rz_mtu3_pwm->channel_data; in rz_mtu3_get_channel()
140 if (priv->map->base_pwm_number + priv->map->num_channel_ios > hwpwm) in rz_mtu3_get_channel()
155 is_channel_en = rz_mtu3_is_enabled(priv->mtu); in rz_mtu3_pwm_is_ch_enabled()
159 if (priv->map->base_pwm_number == hwpwm) in rz_mtu3_pwm_is_ch_enabled()
160 val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TIORH); in rz_mtu3_pwm_is_ch_enabled()
162 val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TIORL); in rz_mtu3_pwm_is_ch_enabled()
174 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_request()
175 ch = priv - rz_mtu3_pwm->channel_data; in rz_mtu3_pwm_request()
177 mutex_lock(&rz_mtu3_pwm->lock); in rz_mtu3_pwm_request()
183 if (!rz_mtu3_pwm->user_count[ch]) { in rz_mtu3_pwm_request()
184 is_mtu3_channel_available = rz_mtu3_request_channel(priv->mtu); in rz_mtu3_pwm_request()
186 mutex_unlock(&rz_mtu3_pwm->lock); in rz_mtu3_pwm_request()
187 return -EBUSY; in rz_mtu3_pwm_request()
191 rz_mtu3_pwm->user_count[ch]++; in rz_mtu3_pwm_request()
192 mutex_unlock(&rz_mtu3_pwm->lock); in rz_mtu3_pwm_request()
203 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_free()
204 ch = priv - rz_mtu3_pwm->channel_data; in rz_mtu3_pwm_free()
206 mutex_lock(&rz_mtu3_pwm->lock); in rz_mtu3_pwm_free()
207 rz_mtu3_pwm->user_count[ch]--; in rz_mtu3_pwm_free()
208 if (!rz_mtu3_pwm->user_count[ch]) in rz_mtu3_pwm_free()
209 rz_mtu3_release_channel(priv->mtu); in rz_mtu3_pwm_free()
211 mutex_unlock(&rz_mtu3_pwm->lock); in rz_mtu3_pwm_free()
222 rc = pm_runtime_resume_and_get(rz_mtu3_pwm->chip.dev); in rz_mtu3_pwm_enable()
226 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_enable()
227 ch = priv - rz_mtu3_pwm->channel_data; in rz_mtu3_pwm_enable()
230 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TMDR1, RZ_MTU3_TMDR1_MD_PWMMODE1); in rz_mtu3_pwm_enable()
231 if (priv->map->base_pwm_number == pwm->hwpwm) in rz_mtu3_pwm_enable()
232 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORH, val); in rz_mtu3_pwm_enable()
234 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORL, val); in rz_mtu3_pwm_enable()
236 mutex_lock(&rz_mtu3_pwm->lock); in rz_mtu3_pwm_enable()
237 if (!rz_mtu3_pwm->enable_count[ch]) in rz_mtu3_pwm_enable()
238 rz_mtu3_enable(priv->mtu); in rz_mtu3_pwm_enable()
240 rz_mtu3_pwm->enable_count[ch]++; in rz_mtu3_pwm_enable()
241 mutex_unlock(&rz_mtu3_pwm->lock); in rz_mtu3_pwm_enable()
252 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_disable()
253 ch = priv - rz_mtu3_pwm->channel_data; in rz_mtu3_pwm_disable()
256 if (priv->map->base_pwm_number == pwm->hwpwm) in rz_mtu3_pwm_disable()
257 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORH, RZ_MTU3_TIOR_OC_RETAIN); in rz_mtu3_pwm_disable()
259 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORL, RZ_MTU3_TIOR_OC_RETAIN); in rz_mtu3_pwm_disable()
261 mutex_lock(&rz_mtu3_pwm->lock); in rz_mtu3_pwm_disable()
262 rz_mtu3_pwm->enable_count[ch]--; in rz_mtu3_pwm_disable()
263 if (!rz_mtu3_pwm->enable_count[ch]) in rz_mtu3_pwm_disable()
264 rz_mtu3_disable(priv->mtu); in rz_mtu3_pwm_disable()
266 mutex_unlock(&rz_mtu3_pwm->lock); in rz_mtu3_pwm_disable()
268 pm_runtime_put_sync(rz_mtu3_pwm->chip.dev); in rz_mtu3_pwm_disable()
277 rc = pm_runtime_resume_and_get(chip->dev); in rz_mtu3_pwm_get_state()
281 state->enabled = rz_mtu3_pwm_is_ch_enabled(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_get_state()
282 if (state->enabled) { in rz_mtu3_pwm_get_state()
288 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_get_state()
289 if (priv->map->base_pwm_number == pwm->hwpwm) in rz_mtu3_pwm_get_state()
296 val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TCR); in rz_mtu3_pwm_get_state()
301 state->period = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate); in rz_mtu3_pwm_get_state()
303 state->duty_cycle = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate); in rz_mtu3_pwm_get_state()
305 if (state->duty_cycle > state->period) in rz_mtu3_pwm_get_state()
306 state->duty_cycle = state->period; in rz_mtu3_pwm_get_state()
309 state->polarity = PWM_POLARITY_NORMAL; in rz_mtu3_pwm_get_state()
310 pm_runtime_put(chip->dev); in rz_mtu3_pwm_get_state()
332 priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); in rz_mtu3_pwm_config()
333 ch = priv - rz_mtu3_pwm->channel_data; in rz_mtu3_pwm_config()
335 period_cycles = mul_u64_u32_div(state->period, rz_mtu3_pwm->rate, in rz_mtu3_pwm_config()
345 if (rz_mtu3_pwm->enable_count[ch] > 1) { in rz_mtu3_pwm_config()
346 if (rz_mtu3_pwm->prescale[ch] > prescale) in rz_mtu3_pwm_config()
347 return -EBUSY; in rz_mtu3_pwm_config()
349 prescale = rz_mtu3_pwm->prescale[ch]; in rz_mtu3_pwm_config()
354 duty_cycles = mul_u64_u32_div(state->duty_cycle, rz_mtu3_pwm->rate, in rz_mtu3_pwm_config()
362 if (!pwm->state.enabled) { in rz_mtu3_pwm_config()
365 rc = pm_runtime_resume_and_get(chip->dev); in rz_mtu3_pwm_config()
373 if (rz_mtu3_pwm->prescale[ch] != prescale && rz_mtu3_pwm->enable_count[ch]) in rz_mtu3_pwm_config()
374 rz_mtu3_disable(priv->mtu); in rz_mtu3_pwm_config()
376 if (priv->map->base_pwm_number == pwm->hwpwm) { in rz_mtu3_pwm_config()
377 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TCR, in rz_mtu3_pwm_config()
382 rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TCR, in rz_mtu3_pwm_config()
388 if (rz_mtu3_pwm->prescale[ch] != prescale) { in rz_mtu3_pwm_config()
394 rz_mtu3_pwm->prescale[ch] = prescale; in rz_mtu3_pwm_config()
396 if (rz_mtu3_pwm->enable_count[ch]) in rz_mtu3_pwm_config()
397 rz_mtu3_enable(priv->mtu); in rz_mtu3_pwm_config()
401 if (!pwm->state.enabled) in rz_mtu3_pwm_config()
402 pm_runtime_put(chip->dev); in rz_mtu3_pwm_config()
411 bool enabled = pwm->state.enabled; in rz_mtu3_pwm_apply()
414 if (state->polarity != PWM_POLARITY_NORMAL) in rz_mtu3_pwm_apply()
415 return -EINVAL; in rz_mtu3_pwm_apply()
417 if (!state->enabled) { in rz_mtu3_pwm_apply()
424 mutex_lock(&rz_mtu3_pwm->lock); in rz_mtu3_pwm_apply()
426 mutex_unlock(&rz_mtu3_pwm->lock); in rz_mtu3_pwm_apply()
448 clk_disable_unprepare(rz_mtu3_pwm->clk); in rz_mtu3_pwm_pm_runtime_suspend()
457 return clk_prepare_enable(rz_mtu3_pwm->clk); in rz_mtu3_pwm_pm_runtime_resume()
468 clk_rate_exclusive_put(rz_mtu3_pwm->clk); in rz_mtu3_pwm_pm_disable()
469 pm_runtime_disable(rz_mtu3_pwm->chip.dev); in rz_mtu3_pwm_pm_disable()
470 pm_runtime_set_suspended(rz_mtu3_pwm->chip.dev); in rz_mtu3_pwm_pm_disable()
475 struct rz_mtu3 *parent_ddata = dev_get_drvdata(pdev->dev.parent); in rz_mtu3_pwm_probe()
477 struct device *dev = &pdev->dev; in rz_mtu3_pwm_probe()
481 rz_mtu3_pwm = devm_kzalloc(&pdev->dev, sizeof(*rz_mtu3_pwm), GFP_KERNEL); in rz_mtu3_pwm_probe()
483 return -ENOMEM; in rz_mtu3_pwm_probe()
485 rz_mtu3_pwm->clk = parent_ddata->clk; in rz_mtu3_pwm_probe()
491 rz_mtu3_pwm->channel_data[j].mtu = &parent_ddata->channels[i]; in rz_mtu3_pwm_probe()
492 rz_mtu3_pwm->channel_data[j].mtu->dev = dev; in rz_mtu3_pwm_probe()
493 rz_mtu3_pwm->channel_data[j].map = &channel_map[j]; in rz_mtu3_pwm_probe()
497 mutex_init(&rz_mtu3_pwm->lock); in rz_mtu3_pwm_probe()
499 ret = clk_prepare_enable(rz_mtu3_pwm->clk); in rz_mtu3_pwm_probe()
503 clk_rate_exclusive_get(rz_mtu3_pwm->clk); in rz_mtu3_pwm_probe()
505 rz_mtu3_pwm->rate = clk_get_rate(rz_mtu3_pwm->clk); in rz_mtu3_pwm_probe()
510 if (rz_mtu3_pwm->rate > NSEC_PER_SEC) { in rz_mtu3_pwm_probe()
511 ret = -EINVAL; in rz_mtu3_pwm_probe()
512 clk_rate_exclusive_put(rz_mtu3_pwm->clk); in rz_mtu3_pwm_probe()
516 pm_runtime_set_active(&pdev->dev); in rz_mtu3_pwm_probe()
517 pm_runtime_enable(&pdev->dev); in rz_mtu3_pwm_probe()
518 rz_mtu3_pwm->chip.dev = &pdev->dev; in rz_mtu3_pwm_probe()
519 ret = devm_add_action_or_reset(&pdev->dev, rz_mtu3_pwm_pm_disable, in rz_mtu3_pwm_probe()
524 rz_mtu3_pwm->chip.ops = &rz_mtu3_pwm_ops; in rz_mtu3_pwm_probe()
525 rz_mtu3_pwm->chip.npwm = RZ_MTU3_MAX_PWM_CHANNELS; in rz_mtu3_pwm_probe()
526 ret = devm_pwmchip_add(&pdev->dev, &rz_mtu3_pwm->chip); in rz_mtu3_pwm_probe()
528 return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n"); in rz_mtu3_pwm_probe()
530 pm_runtime_idle(&pdev->dev); in rz_mtu3_pwm_probe()
535 clk_disable_unprepare(rz_mtu3_pwm->clk); in rz_mtu3_pwm_probe()
541 .name = "pwm-rz-mtu3",
549 MODULE_ALIAS("platform:pwm-rz-mtu3");