Lines Matching +full:tpu +full:- +full:r8a7740
1 // SPDX-License-Identifier: GPL-2.0
3 * R-Mobile TPU PWM driver
72 struct tpu_device *tpu; member
73 unsigned int channel; /* Channel number in the TPU */
94 void __iomem *base = tpd->tpu->base + TPU_CHANNEL_OFFSET in tpu_pwm_write()
95 + tpd->channel * TPU_CHANNEL_SIZE; in tpu_pwm_write()
105 dev_dbg(&tpd->tpu->pdev->dev, "%u: configuring pin as %s\n", in tpu_pwm_set_pin()
106 tpd->channel, states[state]); in tpu_pwm_set_pin()
111 tpd->polarity == PWM_POLARITY_INVERSED ? in tpu_pwm_set_pin()
116 tpd->polarity == PWM_POLARITY_INVERSED ? in tpu_pwm_set_pin()
121 tpd->polarity == PWM_POLARITY_INVERSED ? in tpu_pwm_set_pin()
132 spin_lock_irqsave(&tpd->tpu->lock, flags); in tpu_pwm_start_stop()
133 value = ioread16(tpd->tpu->base + TPU_TSTR); in tpu_pwm_start_stop()
136 value |= 1 << tpd->channel; in tpu_pwm_start_stop()
138 value &= ~(1 << tpd->channel); in tpu_pwm_start_stop()
140 iowrite16(value, tpd->tpu->base + TPU_TSTR); in tpu_pwm_start_stop()
141 spin_unlock_irqrestore(&tpd->tpu->lock, flags); in tpu_pwm_start_stop()
148 if (!tpd->timer_on) { in tpu_pwm_timer_start()
150 pm_runtime_get_sync(&tpd->tpu->pdev->dev); in tpu_pwm_timer_start()
151 ret = clk_prepare_enable(tpd->tpu->clk); in tpu_pwm_timer_start()
153 dev_err(&tpd->tpu->pdev->dev, "cannot enable clock\n"); in tpu_pwm_timer_start()
156 tpd->timer_on = true; in tpu_pwm_timer_start()
168 * - Clear TCNT on TGRB match in tpu_pwm_timer_start()
169 * - Count on rising edge in tpu_pwm_timer_start()
170 * - Set prescaler in tpu_pwm_timer_start()
171 * - Output 0 until TGRA, output 1 until TGRB (active low polarity) in tpu_pwm_timer_start()
172 * - Output 1 until TGRA, output 0 until TGRB (active high polarity in tpu_pwm_timer_start()
173 * - PWM mode in tpu_pwm_timer_start()
176 tpd->prescaler); in tpu_pwm_timer_start()
179 tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty); in tpu_pwm_timer_start()
180 tpu_pwm_write(tpd, TPU_TGRBn, tpd->period); in tpu_pwm_timer_start()
182 dev_dbg(&tpd->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n", in tpu_pwm_timer_start()
183 tpd->channel, tpd->duty, tpd->period); in tpu_pwm_timer_start()
193 if (!tpd->timer_on) in tpu_pwm_timer_stop()
200 clk_disable_unprepare(tpd->tpu->clk); in tpu_pwm_timer_stop()
201 pm_runtime_put(&tpd->tpu->pdev->dev); in tpu_pwm_timer_stop()
203 tpd->timer_on = false; in tpu_pwm_timer_stop()
206 /* -----------------------------------------------------------------------------
212 struct tpu_device *tpu = to_tpu_device(chip); in tpu_pwm_request() local
215 if (pwm->hwpwm >= TPU_CHANNEL_MAX) in tpu_pwm_request()
216 return -EINVAL; in tpu_pwm_request()
220 return -ENOMEM; in tpu_pwm_request()
222 tpd->tpu = tpu; in tpu_pwm_request()
223 tpd->channel = pwm->hwpwm; in tpu_pwm_request()
224 tpd->polarity = PWM_POLARITY_NORMAL; in tpu_pwm_request()
225 tpd->prescaler = 0; in tpu_pwm_request()
226 tpd->period = 0; in tpu_pwm_request()
227 tpd->duty = 0; in tpu_pwm_request()
229 tpd->timer_on = false; in tpu_pwm_request()
248 struct tpu_device *tpu = to_tpu_device(chip); in tpu_pwm_config() local
256 clk_rate = clk_get_rate(tpu->clk); in tpu_pwm_config()
264 return -EINVAL; in tpu_pwm_config()
276 * prescaler = max(ilog2(period) / 2, 7) - 7; in tpu_pwm_config()
299 return -EINVAL; in tpu_pwm_config()
310 dev_dbg(&tpu->pdev->dev, in tpu_pwm_config()
314 if (tpd->prescaler == prescaler && tpd->period == period) in tpu_pwm_config()
317 tpd->prescaler = prescaler; in tpu_pwm_config()
318 tpd->period = period; in tpu_pwm_config()
319 tpd->duty = duty; in tpu_pwm_config()
325 if (duty_only && tpd->timer_on) { in tpu_pwm_config()
331 tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty); in tpu_pwm_config()
332 dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", tpd->channel, in tpu_pwm_config()
333 tpd->duty); in tpu_pwm_config()
358 tpd->polarity = polarity; in tpu_pwm_set_polarity()
376 if (tpd->duty == 0 || tpd->duty == tpd->period) { in tpu_pwm_enable()
377 tpu_pwm_set_pin(tpd, tpd->duty ? in tpu_pwm_enable()
399 bool enabled = pwm->state.enabled; in tpu_pwm_apply()
401 if (state->polarity != pwm->state.polarity) { in tpu_pwm_apply()
407 err = tpu_pwm_set_polarity(chip, pwm, state->polarity); in tpu_pwm_apply()
412 if (!state->enabled) { in tpu_pwm_apply()
419 err = tpu_pwm_config(pwm->chip, pwm, in tpu_pwm_apply()
420 state->duty_cycle, state->period, enabled); in tpu_pwm_apply()
437 /* -----------------------------------------------------------------------------
443 struct tpu_device *tpu; in tpu_probe() local
446 tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL); in tpu_probe()
447 if (tpu == NULL) in tpu_probe()
448 return -ENOMEM; in tpu_probe()
450 spin_lock_init(&tpu->lock); in tpu_probe()
451 tpu->pdev = pdev; in tpu_probe()
454 tpu->base = devm_platform_ioremap_resource(pdev, 0); in tpu_probe()
455 if (IS_ERR(tpu->base)) in tpu_probe()
456 return PTR_ERR(tpu->base); in tpu_probe()
458 tpu->clk = devm_clk_get(&pdev->dev, NULL); in tpu_probe()
459 if (IS_ERR(tpu->clk)) in tpu_probe()
460 return dev_err_probe(&pdev->dev, PTR_ERR(tpu->clk), "Failed to get clock\n"); in tpu_probe()
463 platform_set_drvdata(pdev, tpu); in tpu_probe()
465 tpu->chip.dev = &pdev->dev; in tpu_probe()
466 tpu->chip.ops = &tpu_pwm_ops; in tpu_probe()
467 tpu->chip.npwm = TPU_CHANNEL_MAX; in tpu_probe()
469 ret = devm_pm_runtime_enable(&pdev->dev); in tpu_probe()
471 return dev_err_probe(&pdev->dev, ret, "Failed to enable runtime PM\n"); in tpu_probe()
473 ret = devm_pwmchip_add(&pdev->dev, &tpu->chip); in tpu_probe()
475 return dev_err_probe(&pdev->dev, ret, "Failed to register PWM chip\n"); in tpu_probe()
482 { .compatible = "renesas,tpu-r8a73a4", },
483 { .compatible = "renesas,tpu-r8a7740", },
484 { .compatible = "renesas,tpu-r8a7790", },
485 { .compatible = "renesas,tpu", },
495 .name = "renesas-tpu-pwm",
503 MODULE_DESCRIPTION("Renesas TPU PWM Driver");
505 MODULE_ALIAS("platform:renesas-tpu-pwm");