Lines Matching +full:mt8173 +full:- +full:disp +full:- +full:pwm
1 // SPDX-License-Identifier: GPL-2.0-only
3 * MediaTek display pulse-width-modulation controller driver.
15 #include <linux/pwm.h>
25 #define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
61 void __iomem *address = mdp->base + offset; in mtk_disp_pwm_update_bits()
70 static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in mtk_disp_pwm_apply() argument
78 if (state->polarity != PWM_POLARITY_NORMAL) in mtk_disp_pwm_apply()
79 return -EINVAL; in mtk_disp_pwm_apply()
81 if (!state->enabled && mdp->enabled) { in mtk_disp_pwm_apply()
83 mdp->data->enable_mask, 0x0); in mtk_disp_pwm_apply()
84 clk_disable_unprepare(mdp->clk_mm); in mtk_disp_pwm_apply()
85 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_apply()
87 mdp->enabled = false; in mtk_disp_pwm_apply()
91 if (!mdp->enabled) { in mtk_disp_pwm_apply()
92 err = clk_prepare_enable(mdp->clk_main); in mtk_disp_pwm_apply()
94 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", in mtk_disp_pwm_apply()
99 err = clk_prepare_enable(mdp->clk_mm); in mtk_disp_pwm_apply()
101 dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", in mtk_disp_pwm_apply()
103 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_apply()
115 * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1 in mtk_disp_pwm_apply()
118 rate = clk_get_rate(mdp->clk_main); in mtk_disp_pwm_apply()
119 clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >> in mtk_disp_pwm_apply()
122 if (!mdp->enabled) { in mtk_disp_pwm_apply()
123 clk_disable_unprepare(mdp->clk_mm); in mtk_disp_pwm_apply()
124 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_apply()
126 return -EINVAL; in mtk_disp_pwm_apply()
130 period = mul_u64_u64_div_u64(state->period, rate, div); in mtk_disp_pwm_apply()
132 period--; in mtk_disp_pwm_apply()
134 high_width = mul_u64_u64_div_u64(state->duty_cycle, rate, div); in mtk_disp_pwm_apply()
137 if (mdp->data->bls_debug && !mdp->data->has_commit) { in mtk_disp_pwm_apply()
142 mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug, in mtk_disp_pwm_apply()
143 mdp->data->bls_debug_mask, in mtk_disp_pwm_apply()
144 mdp->data->bls_debug_mask); in mtk_disp_pwm_apply()
145 mtk_disp_pwm_update_bits(mdp, mdp->data->con0, in mtk_disp_pwm_apply()
146 mdp->data->con0_sel, in mtk_disp_pwm_apply()
147 mdp->data->con0_sel); in mtk_disp_pwm_apply()
150 mtk_disp_pwm_update_bits(mdp, mdp->data->con0, in mtk_disp_pwm_apply()
153 mtk_disp_pwm_update_bits(mdp, mdp->data->con1, in mtk_disp_pwm_apply()
157 if (mdp->data->has_commit) { in mtk_disp_pwm_apply()
158 mtk_disp_pwm_update_bits(mdp, mdp->data->commit, in mtk_disp_pwm_apply()
159 mdp->data->commit_mask, in mtk_disp_pwm_apply()
160 mdp->data->commit_mask); in mtk_disp_pwm_apply()
161 mtk_disp_pwm_update_bits(mdp, mdp->data->commit, in mtk_disp_pwm_apply()
162 mdp->data->commit_mask, in mtk_disp_pwm_apply()
166 mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, in mtk_disp_pwm_apply()
167 mdp->data->enable_mask); in mtk_disp_pwm_apply()
168 mdp->enabled = true; in mtk_disp_pwm_apply()
174 struct pwm_device *pwm, in mtk_disp_pwm_get_state() argument
182 err = clk_prepare_enable(mdp->clk_main); in mtk_disp_pwm_get_state()
184 dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); in mtk_disp_pwm_get_state()
188 err = clk_prepare_enable(mdp->clk_mm); in mtk_disp_pwm_get_state()
190 dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err)); in mtk_disp_pwm_get_state()
191 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_get_state()
200 if (mdp->data->bls_debug) in mtk_disp_pwm_get_state()
201 mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug, in mtk_disp_pwm_get_state()
202 mdp->data->bls_debug_mask, in mtk_disp_pwm_get_state()
203 mdp->data->bls_debug_mask); in mtk_disp_pwm_get_state()
205 rate = clk_get_rate(mdp->clk_main); in mtk_disp_pwm_get_state()
206 con0 = readl(mdp->base + mdp->data->con0); in mtk_disp_pwm_get_state()
207 con1 = readl(mdp->base + mdp->data->con1); in mtk_disp_pwm_get_state()
208 pwm_en = readl(mdp->base + DISP_PWM_EN); in mtk_disp_pwm_get_state()
209 state->enabled = !!(pwm_en & mdp->data->enable_mask); in mtk_disp_pwm_get_state()
216 state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate); in mtk_disp_pwm_get_state()
218 state->duty_cycle = DIV64_U64_ROUND_UP(high_width * (clk_div + 1) * NSEC_PER_SEC, in mtk_disp_pwm_get_state()
220 state->polarity = PWM_POLARITY_NORMAL; in mtk_disp_pwm_get_state()
221 clk_disable_unprepare(mdp->clk_mm); in mtk_disp_pwm_get_state()
222 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_get_state()
238 mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL); in mtk_disp_pwm_probe()
240 return -ENOMEM; in mtk_disp_pwm_probe()
242 mdp->data = of_device_get_match_data(&pdev->dev); in mtk_disp_pwm_probe()
244 mdp->base = devm_platform_ioremap_resource(pdev, 0); in mtk_disp_pwm_probe()
245 if (IS_ERR(mdp->base)) in mtk_disp_pwm_probe()
246 return PTR_ERR(mdp->base); in mtk_disp_pwm_probe()
248 mdp->clk_main = devm_clk_get(&pdev->dev, "main"); in mtk_disp_pwm_probe()
249 if (IS_ERR(mdp->clk_main)) in mtk_disp_pwm_probe()
250 return PTR_ERR(mdp->clk_main); in mtk_disp_pwm_probe()
252 mdp->clk_mm = devm_clk_get(&pdev->dev, "mm"); in mtk_disp_pwm_probe()
253 if (IS_ERR(mdp->clk_mm)) in mtk_disp_pwm_probe()
254 return PTR_ERR(mdp->clk_mm); in mtk_disp_pwm_probe()
256 mdp->chip.dev = &pdev->dev; in mtk_disp_pwm_probe()
257 mdp->chip.ops = &mtk_disp_pwm_ops; in mtk_disp_pwm_probe()
258 mdp->chip.npwm = 1; in mtk_disp_pwm_probe()
260 ret = pwmchip_add(&mdp->chip); in mtk_disp_pwm_probe()
262 dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret)); in mtk_disp_pwm_probe()
275 pwmchip_remove(&mdp->chip); in mtk_disp_pwm_remove()
309 { .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
310 { .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
311 { .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
312 { .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
319 .name = "mediatek-disp-pwm",
328 MODULE_DESCRIPTION("MediaTek SoC display PWM driver");